mirror of https://github.com/YosysHQ/yosys.git
Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and `outbit_to_cell`.
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@ -101,7 +101,7 @@ struct TechmapWorker
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std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
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{
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std::string constmap_info;
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std::map<RTLIL::SigBit, std::pair<IdString, int>> connbits_map;
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dict<RTLIL::SigBit, std::pair<IdString, int>> connbits_map;
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for (auto conn : cell->connections())
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for (int i = 0; i < GetSize(conn.second); i++) {
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@ -490,8 +490,8 @@ struct TechmapWorker
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}
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TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
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std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
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std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
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dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
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dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
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for (auto cell : module->selected_cells())
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{
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