mirror of https://github.com/YosysHQ/yosys.git
abc9_ops -reintegrate: process box connections
This commit is contained in:
Eddie Hung
parent
61a2a60595
commit
dc3b21c1c0
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@ -437,6 +437,57 @@ void reintegrate(RTLIL::Module *module)
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for (auto w : mapped_mod->wires())
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module->addWire(remap_name(w->name), GetSize(w));
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dict<IdString,IdString> box_lookup;
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dict<IdString,std::vector<IdString>> box_ports;
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for (auto m : design->modules()) {
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auto it = m->attributes.find(ID(abc9_box_id));
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if (it == m->attributes.end())
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continue;
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if (m->name.begins_with("$paramod"))
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continue;
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auto id = it->second.as_int();
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auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
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if (!r.second)
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log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
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log_id(m), id, log_id(r.first->second));
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log_assert(r.second);
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auto r2 = box_ports.insert(m->name);
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if (r2.second) {
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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for (const auto &port_name : m->ports) {
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auto w = m->wire(port_name);
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log_assert(w);
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input) {
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if (carry_in != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
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carry_in = port_name;
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}
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if (w->port_output) {
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if (carry_out != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(m));
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carry_out = port_name;
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}
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}
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else
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r2.first->second.push_back(port_name);
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}
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if (carry_in != IdString() && carry_out == IdString())
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log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
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if (carry_in != IdString()) {
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r2.first->second.push_back(carry_in);
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r2.first->second.push_back(carry_out);
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}
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}
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}
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for (auto it = module->cells_.begin(); it != module->cells_.end(); )
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if (it->second->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_)))
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it = module->cells_.erase(it);
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@ -515,42 +566,98 @@ void reintegrate(RTLIL::Module *module)
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else {
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existing_cell = module->cell(mapped_cell->name);
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log_assert(existing_cell);
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if (mapped_cell->type.begins_with("$__boxid")) {
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auto type = box_lookup.at(mapped_cell->type, IdString());
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if (type == IdString())
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log_error("No module with abc9_box_id = %s found.\n", mapped_cell->type.c_str() + strlen("$__boxid"));
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mapped_cell->type = type;
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}
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cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
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}
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RTLIL::Module* box_module = design->module(mapped_cell->type);
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auto abc9_flop = box_module && box_module->attributes.count("\\abc9_flop");
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for (auto &mapped_conn : mapped_cell->connections()) {
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RTLIL::SigSpec newsig;
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for (auto c : mapped_conn.second.chunks()) {
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if (c.width == 0)
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continue;
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//log_assert(c.width == 1);
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if (c.wire)
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c.wire = module->wires_.at(remap_name(c.wire->name));
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newsig.append(c);
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if (existing_cell) {
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auto it = mapped_cell->connections_.find("\\i");
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log_assert(it != mapped_cell->connections_.end());
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SigSpec inputs = std::move(it->second);
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mapped_cell->connections_.erase(it);
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it = mapped_cell->connections_.find("\\o");
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log_assert(it != mapped_cell->connections_.end());
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SigSpec outputs = std::move(it->second);
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mapped_cell->connections_.erase(it);
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RTLIL::Module* box_module = design->module(mapped_cell->type);
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auto abc9_flop = box_module->attributes.count("\\abc9_flop");
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if (!abc9_flop) {
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for (const auto &i : inputs)
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bit_users[i].insert(mapped_cell->name);
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for (const auto &i : outputs)
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bit_drivers[i].insert(mapped_cell->name);
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}
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if (existing_cell) {
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auto it = existing_cell->connections_.find(mapped_conn.first);
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int input_count = 0, output_count = 0;
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for (const auto &port_name : box_ports.at(cell->type)) {
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RTLIL::Wire *w = box_module->wire(port_name);
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log_assert(w);
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SigSpec sig;
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if (w->port_input) {
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sig = inputs.extract(input_count, GetSize(w));
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input_count += GetSize(w);
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}
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if (w->port_output) {
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sig = outputs.extract(output_count, GetSize(w));
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output_count += GetSize(w);
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}
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SigSpec newsig;
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for (auto c : sig.chunks()) {
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if (c.width == 0)
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continue;
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//log_assert(c.width == 1);
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if (c.wire)
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c.wire = module->wires_.at(remap_name(c.wire->name));
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newsig.append(c);
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}
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auto it = existing_cell->connections_.find(port_name);
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if (it == existing_cell->connections_.end())
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continue;
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log_assert(GetSize(newsig) >= GetSize(it->second));
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newsig = newsig.extract(0, GetSize(it->second));
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}
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cell->setPort(mapped_conn.first, newsig);
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if (GetSize(newsig) > GetSize(it->second))
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newsig = newsig.extract(0, GetSize(it->second));
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else
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log_assert(GetSize(newsig) == GetSize(it->second));
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if (abc9_flop)
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continue;
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cell->setPort(port_name, newsig);
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if (cell->input(mapped_conn.first)) {
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for (auto i : newsig)
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bit2sinks[i].push_back(cell);
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for (auto i : mapped_conn.second)
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bit_users[i].insert(mapped_cell->name);
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if (w->port_input && !abc9_flop)
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for (const auto &i : newsig)
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bit2sinks[i].push_back(cell);
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}
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}
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else {
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for (auto &mapped_conn : mapped_cell->connections()) {
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RTLIL::SigSpec newsig;
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for (auto c : mapped_conn.second.chunks()) {
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if (c.width == 0)
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continue;
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//log_assert(c.width == 1);
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if (c.wire)
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c.wire = module->wires_.at(remap_name(c.wire->name));
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newsig.append(c);
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}
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cell->setPort(mapped_conn.first, newsig);
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if (cell->input(mapped_conn.first)) {
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for (auto i : newsig)
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bit2sinks[i].push_back(cell);
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for (auto i : mapped_conn.second)
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bit_users[i].insert(mapped_cell->name);
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}
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if (cell->output(mapped_conn.first))
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for (auto i : mapped_conn.second)
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bit_drivers[i].insert(mapped_cell->name);
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}
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if (cell->output(mapped_conn.first))
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for (auto i : mapped_conn.second)
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bit_drivers[i].insert(mapped_cell->name);
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}
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if (existing_cell) {
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