mirror of https://github.com/YosysHQ/yosys.git
read_aiger: do not process box connections, work standalone
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6e12ba218b
commit
61a2a60595
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@ -382,21 +382,6 @@ void AigerReader::parse_xaiger()
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if (f.peek() == '\n')
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f.get();
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dict<int,IdString> box_lookup;
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for (auto m : design->modules()) {
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auto it = m->attributes.find(ID(abc9_box_id));
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if (it == m->attributes.end())
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continue;
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if (m->name.begins_with("$paramod"))
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continue;
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auto id = it->second.as_int();
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auto r = box_lookup.insert(std::make_pair(id, m->name));
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if (!r.second)
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log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
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log_id(m), id, log_id(r.first->second));
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log_assert(r.second);
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}
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// Parse footer (symbol table, comments, etc.)
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std::string s;
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for (int c = f.get(); c != EOF; c = f.get()) {
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@ -467,11 +452,14 @@ void AigerReader::parse_xaiger()
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uint32_t boxNum = parse_xaiger_literal(f);
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log_debug("boxNum = %u\n", boxNum);
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for (unsigned i = 0; i < boxNum; i++) {
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f.ignore(2*sizeof(uint32_t));
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uint32_t boxInputs = parse_xaiger_literal(f);
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uint32_t boxOutputs = parse_xaiger_literal(f);
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uint32_t boxUniqueId = parse_xaiger_literal(f);
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log_assert(boxUniqueId > 0);
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uint32_t oldBoxNum = parse_xaiger_literal(f);
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RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), box_lookup.at(boxUniqueId));
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RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), stringf("$__boxid%u", boxUniqueId));
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cell->setPort("\\i", SigSpec(State::S0, boxInputs));
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cell->setPort("\\o", SigSpec(State::S0, boxOutputs));
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boxes.emplace_back(cell);
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}
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}
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@ -501,7 +489,8 @@ void AigerReader::parse_aiger_ascii()
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as an input!\n", line_count);
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log_debug2("%d is an input\n", l1);
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RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, l1));
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log_assert(!(l1 & 1)); // Inputs can't be inverted
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RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, i));
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wire->port_input = true;
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module->connect(createWireIfNotExists(module, l1 << 1), wire);
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inputs.push_back(wire);
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@ -576,6 +565,8 @@ void AigerReader::parse_aiger_ascii()
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wire->port_output = true;
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bad_properties.push_back(wire);
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}
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if (B > 0)
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std::getline(f, line); // Ignore up to start of next line
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// TODO: Parse invariant constraints
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for (unsigned i = 0; i < C; ++i, ++line_count)
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@ -729,84 +720,46 @@ void AigerReader::parse_aiger_binary()
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void AigerReader::post_process()
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{
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dict<IdString, std::vector<IdString>> box_ports;
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unsigned ci_count = 0, co_count = 0, flop_count = 0;
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unsigned ci_count = 0, co_count = 0;
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for (auto cell : boxes) {
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RTLIL::Module* box_module = design->module(cell->type);
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log_assert(box_module);
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auto r = box_ports.insert(cell->type);
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if (r.second) {
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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for (const auto &port_name : box_module->ports) {
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auto w = box_module->wire(port_name);
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log_assert(w);
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input)
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carry_in = port_name;
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if (w->port_output)
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carry_out = port_name;
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}
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else
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r.first->second.push_back(port_name);
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}
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if (carry_in != IdString()) {
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log_assert(carry_out != IdString());
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r.first->second.push_back(carry_in);
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r.first->second.push_back(carry_out);
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}
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}
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for (auto port_name : box_ports.at(cell->type)) {
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RTLIL::Wire* port = box_module->wire(port_name);
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log_assert(port);
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RTLIL::SigSpec rhs;
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for (int i = 0; i < GetSize(port); i++) {
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RTLIL::Wire* wire = nullptr;
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if (port->port_input) {
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log_assert(co_count < outputs.size());
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wire = outputs[co_count++];
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log_assert(wire);
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log_assert(wire->port_output);
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wire->port_output = false;
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}
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if (port->port_output) {
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log_assert((piNum + ci_count) < inputs.size());
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wire = inputs[piNum + ci_count++];
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log_assert(wire);
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log_assert(wire->port_input);
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wire->port_input = false;
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}
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rhs.append(wire);
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}
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cell->setPort(port_name, rhs);
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}
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if (box_module->attributes.count("\\abc9_flop")) {
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for (auto &bit : cell->connections_.at("\\i")) {
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log_assert(bit == State::S0);
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log_assert(co_count < outputs.size());
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Wire *wire = outputs[co_count++];
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log_assert(wire);
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log_assert(wire->port_output);
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wire->port_output = false;
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RTLIL::Wire *d = outputs[outputs.size() - flopNum + flop_count];
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log_assert(d);
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log_assert(d->port_output);
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d->port_output = false;
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RTLIL::Wire *q = inputs[piNum - flopNum + flop_count];
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log_assert(q);
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log_assert(q->port_input);
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q->port_input = false;
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auto ff = module->addCell(NEW_ID, "$__ABC9_FF_");
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ff->setPort("\\D", d);
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ff->setPort("\\Q", q);
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flop_count++;
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continue;
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bit = outputs[co_count++];
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log_assert(bit.wire && GetSize(bit.wire) == 1);
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log_assert(bit.wire->port_output);
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bit.wire->port_output = false;
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}
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for (auto &bit : cell->connections_.at("\\o")) {
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log_assert(bit == State::S0);
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log_assert((piNum + ci_count) < inputs.size());
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bit = inputs[piNum + ci_count++];
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log_assert(bit.wire && GetSize(bit.wire) == 1);
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log_assert(bit.wire->port_input);
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bit.wire->port_input = false;
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}
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}
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for (uint32_t i = 0; i < flopNum; i++) {
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log_assert(co_count < outputs.size());
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Wire *wire = outputs[co_count++];
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log_assert(wire);
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log_assert(wire->port_output);
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wire->port_output = false;
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RTLIL::Wire *d = outputs[outputs.size() - flopNum + i];
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log_assert(d);
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log_assert(d->port_output);
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d->port_output = false;
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RTLIL::Wire *q = inputs[piNum - flopNum + i];
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log_assert(q);
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log_assert(q->port_input);
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q->port_input = false;
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auto ff = module->addCell(NEW_ID, "$__ABC9_FF_");
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ff->setPort("\\D", d);
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ff->setPort("\\Q", q);
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}
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dict<RTLIL::IdString, int> wideports_cache;
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@ -856,10 +809,6 @@ void AigerReader::post_process()
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RTLIL::Wire* wire = outputs[variable + co_count];
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log_assert(wire);
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log_assert(wire->port_output);
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if (escaped_s == "$__dummy__") {
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wire->port_output = false;
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continue;
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}
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log_debug("Renaming output %s", log_id(wire));
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if (index == 0) {
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@ -897,26 +846,8 @@ void AigerReader::post_process()
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}
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else if (type == "box") {
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RTLIL::Cell* cell = module->cell(stringf("$box%d", variable));
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if (cell) { // ABC could have optimised this box away
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if (cell) // ABC could have optimised this box away
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module->rename(cell, escaped_s);
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for (const auto &i : cell->connections()) {
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RTLIL::IdString port_name = i.first;
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RTLIL::SigSpec rhs = i.second;
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int index = 0;
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for (auto bit : rhs.bits()) {
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RTLIL::Wire* wire = bit.wire;
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RTLIL::IdString escaped_s = RTLIL::escape_id(stringf("%s.%s", log_id(cell), log_id(port_name)));
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if (index == 0)
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module->rename(wire, escaped_s);
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else if (index > 0) {
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module->rename(wire, stringf("%s[%d]", escaped_s.c_str(), index));
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if (wideports)
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wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
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}
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index++;
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}
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}
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}
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}
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else
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log_error("Symbol type '%s' not recognised.\n", type.c_str());
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