mirror of https://github.com/YosysHQ/yosys.git
Preserve topo ordering from -prep_holes to write_xaiger
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bb70915fb8
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559f3379e8
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@ -78,7 +78,7 @@ struct XAigerWriter
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Module *module;
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SigMap sigmap;
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pool<SigBit> input_bits, output_bits, external_bits;
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pool<SigBit> input_bits, output_bits;
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dict<SigBit, SigBit> not_map, alias_map;
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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vector<SigBit> ci_bits, co_bits;
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@ -199,12 +199,6 @@ struct XAigerWriter
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}
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}
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// TODO: Speed up toposort -- ultimately we care about
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// box ordering, but not individual AIG cells
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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bool abc9_box_seen = false;
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for (auto cell : module->selected_cells()) {
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if (cell->type == "$_NOT_")
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{
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@ -213,9 +207,6 @@ struct XAigerWriter
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unused_bits.erase(A);
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undriven_bits.erase(Y);
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not_map[Y] = A;
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toposort.node(cell->name);
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bit_users[A].insert(cell->name);
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bit_drivers[Y].insert(cell->name);
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continue;
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}
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@ -228,10 +219,6 @@ struct XAigerWriter
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unused_bits.erase(B);
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undriven_bits.erase(Y);
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and_map[Y] = make_pair(A, B);
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toposort.node(cell->name);
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bit_users[A].insert(cell->name);
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bit_users[B].insert(cell->name);
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bit_drivers[Y].insert(cell->name);
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continue;
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}
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@ -257,22 +244,17 @@ struct XAigerWriter
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if (abc9_box && cell->get_bool_attribute("\\abc9_keep"))
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abc9_box = false;
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if (abc9_box) {
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int abc9_box_order = cell->attributes.at("\\abc9_box_order").as_int();
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if (GetSize(box_list) <= abc9_box_order)
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box_list.resize(abc9_box_order+1);
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box_list[abc9_box_order] = cell;
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if (!abc9_flop)
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continue;
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}
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for (const auto &conn : cell->connections()) {
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auto port_wire = inst_module->wire(conn.first);
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if (abc9_box) {
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// Ignore inout for the sake of topographical ordering
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if (port_wire->port_input && !port_wire->port_output)
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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if (port_wire->port_output)
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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if (!abc9_flop)
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continue;
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}
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if (port_wire->port_output) {
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int arrival = 0;
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auto it = port_wire->attributes.find("\\abc9_arrival");
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@ -286,12 +268,6 @@ struct XAigerWriter
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arrival_times[bit] = arrival;
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}
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}
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if (abc9_box) {
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abc9_box_seen = true;
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toposort.node(cell->name);
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continue;
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}
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}
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bool cell_known = inst_module || cell->known();
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@ -319,138 +295,56 @@ struct XAigerWriter
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//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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}
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if (abc9_box_seen) {
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for (auto &it : bit_users)
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if (bit_drivers.count(it.first))
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for (auto driver_cell : bit_drivers.at(it.first))
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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for (auto cell : box_list) {
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log_assert(cell);
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#if 0
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toposort.analyze_loops = true;
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#endif
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bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
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#if 0
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unsigned i = 0;
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for (auto &it : toposort.loops) {
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log(" loop %d\n", i++);
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for (auto cell_name : it) {
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auto cell = module->cell(cell_name);
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log_assert(cell);
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log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
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}
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}
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#endif
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log_assert(no_loops);
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RTLIL::Module* box_module = module->design->module(cell->type);
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log_assert(box_module);
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log_assert(box_module->attributes.count("\\abc9_box_id"));
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for (auto cell_name : toposort.sorted) {
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RTLIL::Cell *cell = module->cell(cell_name);
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log_assert(cell);
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RTLIL::Module* box_module = module->design->module(cell->type);
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if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
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continue;
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bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
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auto r = box_ports.insert(cell->type);
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if (r.second) {
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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for (const auto &port_name : box_module->ports) {
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auto w = box_module->wire(port_name);
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log_assert(w);
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input) {
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if (carry_in != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
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carry_in = port_name;
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}
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if (w->port_output) {
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if (carry_out != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
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carry_out = port_name;
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}
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}
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else
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r.first->second.push_back(port_name);
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}
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if (carry_in != IdString() && carry_out == IdString())
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log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
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if (carry_in != IdString()) {
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r.first->second.push_back(carry_in);
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r.first->second.push_back(carry_out);
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}
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}
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// Fully pad all unused input connections of this box cell with S0
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// Fully pad all undriven output connections of this box cell with anonymous wires
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for (auto port_name : r.first->second) {
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auto r = box_ports.insert(cell->type);
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if (r.second) {
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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for (const auto &port_name : box_module->ports) {
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auto w = box_module->wire(port_name);
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log_assert(w);
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auto it = cell->connections_.find(port_name);
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if (w->port_input) {
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RTLIL::SigSpec rhs;
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if (it != cell->connections_.end()) {
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if (GetSize(it->second) < GetSize(w))
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it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
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rhs = it->second;
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input) {
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if (carry_in != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
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carry_in = port_name;
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}
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else {
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rhs = RTLIL::SigSpec(State::S0, GetSize(w));
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cell->setPort(port_name, rhs);
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}
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for (auto b : rhs) {
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SigBit I = sigmap(b);
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if (b == RTLIL::Sx)
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b = State::S0;
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else if (I != b) {
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if (I == RTLIL::Sx)
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alias_map[b] = State::S0;
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else
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alias_map[b] = I;
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}
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co_bits.emplace_back(b);
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unused_bits.erase(I);
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}
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}
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if (w->port_output) {
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RTLIL::SigSpec rhs;
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auto it = cell->connections_.find(w->name);
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if (it != cell->connections_.end()) {
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if (GetSize(it->second) < GetSize(w))
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it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
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rhs = it->second;
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}
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else {
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Wire *wire = module->addWire(NEW_ID, GetSize(w));
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if (blackbox)
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wire->set_bool_attribute(ID(abc9_padding));
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rhs = wire;
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cell->setPort(port_name, rhs);
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}
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for (const auto &b : rhs.bits()) {
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SigBit O = sigmap(b);
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if (O != b)
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alias_map[O] = b;
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ci_bits.emplace_back(b);
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undriven_bits.erase(O);
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if (w->port_output) {
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if (carry_out != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
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carry_out = port_name;
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}
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}
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else
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r.first->second.push_back(port_name);
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}
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// Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
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if (box_module->get_bool_attribute("\\abc9_flop")) {
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SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
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if (rhs.empty())
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log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
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if (carry_in != IdString() && carry_out == IdString())
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log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
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if (carry_in != IdString()) {
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r.first->second.push_back(carry_in);
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r.first->second.push_back(carry_out);
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}
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}
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bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
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// Fully pad all unused input connections of this box cell with S0
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// Fully pad all undriven output connections of this box cell with anonymous wires
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for (auto port_name : r.first->second) {
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auto w = box_module->wire(port_name);
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log_assert(w);
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auto rhs = cell->getPort(port_name);
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if (w->port_input)
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for (auto b : rhs) {
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SigBit I = sigmap(b);
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if (b == RTLIL::Sx)
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@ -464,12 +358,36 @@ struct XAigerWriter
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co_bits.emplace_back(b);
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unused_bits.erase(I);
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}
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}
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box_list.emplace_back(cell);
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if (w->port_output)
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for (const auto &b : rhs.bits()) {
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SigBit O = sigmap(b);
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if (O != b)
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alias_map[O] = b;
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ci_bits.emplace_back(b);
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undriven_bits.erase(O);
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}
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}
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// TODO: Free memory from toposort, bit_drivers, bit_users
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// Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
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if (box_module->get_bool_attribute("\\abc9_flop")) {
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SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
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if (rhs.empty())
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log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
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for (auto b : rhs) {
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SigBit I = sigmap(b);
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if (b == RTLIL::Sx)
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b = State::S0;
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else if (I != b) {
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if (I == RTLIL::Sx)
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alias_map[b] = State::S0;
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else
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alias_map[b] = I;
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}
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co_bits.emplace_back(b);
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unused_bits.erase(I);
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}
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}
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}
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for (auto bit : input_bits)
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@ -187,17 +187,13 @@ struct Abc9Pass : public ScriptPass
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{
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run("scc -set_attr abc9_scc_id {}");
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run("abc9_ops -break_scc"/*" -prep_holes"*/);
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// run("select -set abc9_holes A:abc9_holes");
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// run("dump @abc9_holes");
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// run("flatten -wb @abc9_holes");
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// run("techmap @abc9_holes");
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run("aigmap");
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run("abc9_ops -prep_holes");
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if (dff_mode)
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run("abc9_ops -prep_dff");
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// run("opt -purge @abc9_holes");
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run("abc9_ops -prep_holes");
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run("select -set abc9_holes A:abc9_holes");
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run("wbflip @abc9_holes");
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@ -322,6 +322,7 @@ void prep_holes(RTLIL::Module *module)
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}
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}
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cell->attributes["\\abc9_box_order"] = box_list.size();
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box_list.emplace_back(cell);
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}
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log_assert(!box_list.empty());
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