mirror of https://github.com/YosysHQ/yosys.git
Initial skeleton for `qbfsat` command.
This commit is contained in:
Alberto Gonzalez
parent
a0416fe167
commit
fb878b2a70
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@ -13,4 +13,5 @@ OBJS += passes/sat/fmcombine.o
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OBJS += passes/sat/mutate.o
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OBJS += passes/sat/cutpoint.o
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OBJS += passes/sat/fminit.o
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OBJS += passes/sat/qbfsat.o
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@ -0,0 +1,206 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 Alberto Gonzalez <boqwxp@airmail.cc>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct QbfSolutionType {
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std::vector<std::string> stdout;
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bool sat;
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bool unknown; //true if neither 'sat' nor 'unsat'
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bool success; //true if exit code 0
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QbfSolutionType() : sat(false), unknown(true), success(false) {}
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};
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QbfSolutionType qbf_solve(RTLIL::Module *mod) {
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QbfSolutionType ret;
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//TODO: make temporary directory
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//TODO: call `prep`
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//TODO: call `write_smt2`
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//TODO: execute and capture stdout from `yosys-smtbmc`
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//TODO: remove temporary directory
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return ret;
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}
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void print_proof_failed()
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{
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log("\n");
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log(" ______ ___ ___ _ _ _ _ \n");
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log(" (_____ \\ / __) / __) (_) | | | |\n");
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log(" _____) )___ ___ ___ _| |__ _| |__ _____ _| | _____ __| | |\n");
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log(" | ____/ ___) _ \\ / _ (_ __) (_ __|____ | | || ___ |/ _ |_|\n");
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log(" | | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_ \n");
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log(" |_| |_| \\___/ \\___/ |_| |_| \\_____|_|\\_)_____)\\____|_|\n");
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log("\n");
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}
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void print_timeout()
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{
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log("\n");
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log(" _____ _ _ _____ ____ _ _____\n");
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log(" /__ __\\/ \\/ \\__/|/ __// _ \\/ \\ /\\/__ __\\\n");
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log(" / \\ | || |\\/||| \\ | / \\|| | || / \\\n");
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log(" | | | || | ||| /_ | \\_/|| \\_/| | |\n");
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log(" \\_/ \\_/\\_/ \\|\\____\\\\____/\\____/ \\_/\n");
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log("\n");
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}
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void print_qed()
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{
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log("\n");
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log(" /$$$$$$ /$$$$$$$$ /$$$$$$$ \n");
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log(" /$$__ $$ | $$_____/ | $$__ $$ \n");
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log(" | $$ \\ $$ | $$ | $$ \\ $$ \n");
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log(" | $$ | $$ | $$$$$ | $$ | $$ \n");
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log(" | $$ | $$ | $$__/ | $$ | $$ \n");
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log(" | $$/$$ $$ | $$ | $$ | $$ \n");
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log(" | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$\n");
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log(" \\____ $$$|__/|________/|__/|_______/|__/\n");
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log(" \\__/ \n");
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log("\n");
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}
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struct QbfSatPass : public Pass {
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QbfSatPass() : Pass("qbfsat", "solve a 2QBF-SAT problem in the circuit") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" qbfsat [options] [selection]\n");
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log("\n");
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log("This command solves a 2QBF-SAT problem defined over the currently selected module.\n");
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log("Existentially-quantified variables are declared by assigning a wire \"$anyconst\".\n");
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log("Universally-quantified variables may be explicitly declared by assigning a wire\n");
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log("\"$allconst\", but module inputs will be treated as universally-quantified variables\n");
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log("by default.\n");
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log("\n");
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log(" -timeout <seconds>\n");
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log(" Set the solver timeout to the specified number of seconds.\n");
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log("\n");
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log(" -specialize\n");
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log(" Replace all \"$anyconst\" cells with constant values determined by the solver.\n");
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log("\n");
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log(" -specialize-from-file <solution file>\n");
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log(" Do not run the solver, but instead only attempt to replace all \"$anyconst\"\n");
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log(" cells in the current module with values provided by the specified file.\n");
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log("\n");
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log(" -write-solution <solution file>\n");
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log(" Write the assignments discovered by the solver for all \"$anyconst\" cells\n");
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log(" to the specified file.");
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log("\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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bool timeout = false, specialize = false, specialize_from_file = false, write_solution = false;
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long timeout_sec = -1;
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std::string specialize_soln_file;
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std::string write_soln_soln_file;
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log_header(design, "Executing QBF-SAT pass (solving QBF-SAT problems in the circuit).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-timeout") {
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timeout = true;
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if (args.size() <= argidx + 1)
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log_cmd_error("timeout not specified.\n");
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else
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timeout_sec = atol(args[++argidx].c_str());
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continue;
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}
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else if (args[argidx] == "-specialize") {
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specialize = true;
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continue;
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}
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else if (args[argidx] == "-specialize-from-file") {
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specialize_from_file = true;
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if (args.size() <= argidx + 1)
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log_cmd_error("solution file not specified.\n");
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else
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specialize_soln_file = args[++argidx];
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continue;
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}
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else if (args[argidx] == "-write-solution") {
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write_solution = true;
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if (args.size() <= argidx + 1)
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log_cmd_error("solution file not specified.\n");
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else
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write_soln_soln_file = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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RTLIL::Module *module = NULL;
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for (auto mod : design->selected_modules()) {
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if (module)
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log_cmd_error("Only one module must be selected for the QBF-SAT pass! (selected: %s and %s)\n", log_id(module), log_id(mod));
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module = mod;
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}
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if (module == NULL)
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log_cmd_error("Can't perform QBF-SAT on an empty selection!\n");
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bool found_input = false;
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bool found_hole = false;
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bool found_1bit_output = false;
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for (auto wire : module->wires()) {
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if (wire->port_input)
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found_input = true;
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if (wire->port_output && wire->width == 1)
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found_1bit_output = true;
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}
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for (auto cell : module->cells()) {
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if (cell->type == "$allconst")
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found_input = true;
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if (cell->type == "$anyconst")
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found_hole = true;
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if (cell->type.in("$assert", "$assume"))
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found_1bit_output = true;
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}
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if (!found_input)
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log_cmd_error("Can't perform QBF-SAT on a miter with no inputs!\n");
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if (!found_hole)
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log_cmd_error("Did not find any existentially-quantified variables. Use 'sat' instead.\n");
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if (!found_1bit_output)
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log_cmd_error("Did not find any single-bit outputs, assert()s, or assume()s. Is this a miter circuit?\n");
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QbfSolutionType ret = qbf_solve(module);
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if (ret.unknown)
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log_warning("solver did not give an answer\n");
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else if (ret.sat)
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print_qed();
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else
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print_proof_failed();
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//TODO specialize etc.
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}
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} QbfSatPass;
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PRIVATE_NAMESPACE_END
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