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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor

This commit is contained in:
Eddie Hung 2020-01-02 15:14:12 -08:00
parent d597e3e979 f8d5920a7e
commit 5f97086302
40 changed files with 191 additions and 116 deletions
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29
kernel/rtlil.cc
View File

@ -1893,10 +1893,6 @@ DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
DEF_METHOD(Shl, sig_a.size(), ID($shl))
DEF_METHOD(Shr, sig_a.size(), ID($shr))
DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
DEF_METHOD(Shift, sig_a.size(), ID($shift))
DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
DEF_METHOD(Lt, 1, ID($lt))
@ -1916,6 +1912,31 @@ DEF_METHOD(LogicAnd, 1, ID($logic_and))
DEF_METHOD(LogicOr, 1, ID($logic_or))
#undef DEF_METHOD
#define DEF_METHOD(_func, _y_size, _type) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
RTLIL::Cell *cell = addCell(name, _type); \
cell->parameters[ID(A_SIGNED)] = is_signed; \
cell->parameters[ID(B_SIGNED)] = false; \
cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
cell->setPort(ID::A, sig_a); \
cell->setPort(ID::B, sig_b); \
cell->setPort(ID::Y, sig_y); \
cell->set_src_attribute(src); \
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
return sig_y; \
}
DEF_METHOD(Shl, sig_a.size(), ID($shl))
DEF_METHOD(Shr, sig_a.size(), ID($shr))
DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
#undef DEF_METHOD
#define DEF_METHOD(_func, _type, _pmux) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
RTLIL::Cell *cell = addCell(name, _type); \

24
passes/techmap/abc.cc
View File

@ -29,17 +29,17 @@
// Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558-562, doi:10.1145/368996.369025
// http://en.wikipedia.org/wiki/Topological_sorting
#define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; &get -n; &dch -f; &nf {D}; &put"
#define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; dch -f; if; mfs2"
#define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; dch -f; cover {I} {P}"
#define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; &get -n; &dch -f; &nf {D}; &put"
#define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
#define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2"
#define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}"
#define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
#define ABC_FAST_COMMAND_LIB "strash; dretime; retime {D}; map {D}"
#define ABC_FAST_COMMAND_CTR "strash; dretime; retime {D}; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
#define ABC_FAST_COMMAND_LUT "strash; dretime; retime {D}; if"
#define ABC_FAST_COMMAND_SOP "strash; dretime; retime {D}; cover -I {I} -P {P}"
#define ABC_FAST_COMMAND_DFL "strash; dretime; retime {D}; map"
#define ABC_FAST_COMMAND_LIB "strash; dretime; map {D}"
#define ABC_FAST_COMMAND_CTR "strash; dretime; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
#define ABC_FAST_COMMAND_LUT "strash; dretime; if"
#define ABC_FAST_COMMAND_SOP "strash; dretime; cover -I {I} -P {P}"
#define ABC_FAST_COMMAND_DFL "strash; dretime; map"
#include "kernel/register.h"
#include "kernel/sigtools.h"
@ -747,6 +747,10 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
else
abc_script += fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL;
if (script_file.empty() && !delay_target.empty())
for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);

3
passes/techmap/iopadmap.cc
View File

@ -234,6 +234,9 @@ struct IopadmapPass : public Pass {
SigBit wire_bit(wire, i);
Cell *tbuf_cell = nullptr;
if (skip_wire_bits.count(wire_bit))
continue;
if (tbuf_bits.count(wire_bit))
tbuf_cell = tbuf_bits.at(wire_bit);

6
techlibs/achronix/synth_achronix.cc
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@ -52,7 +52,7 @@ struct SynthAchronixPass : public ScriptPass {
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -152,12 +152,12 @@ struct SynthAchronixPass : public ScriptPass {
run("clean -purge");
run("setundef -undriven -zero");
if (retime || help_mode)
run("abc -markgroups -dff", "(only if -retime)");
run("abc -markgroups -dff -D 1", "(only if -retime)");
}
if (check_label("map_luts"))
{
run("abc -lut 4" + string(retime ? " -dff" : ""));
run("abc -lut 4" + string(retime ? " -dff -D 1" : ""));
run("clean");
}

6
techlibs/anlogic/Makefile.inc
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@ -7,6 +7,6 @@ $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/dram_init_16x4.vh))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutram_init_16x4.vh))

16
techlibs/anlogic/cells_map.v
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@ -6,14 +6,14 @@ module \$_DFFE_NP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REG
module \$_DFFE_PN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule
module \$_DFFE_PP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule
module \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule
module \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule
module \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
module \$_DLATCH_N_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";

0
techlibs/anlogic/dram_init_16x4.vh → techlibs/anlogic/lutram_init_16x4.vh
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0
techlibs/anlogic/drams.txt → techlibs/anlogic/lutrams.txt
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2
techlibs/anlogic/drams_map.v → techlibs/anlogic/lutrams_map.v
View File

@ -10,7 +10,7 @@ module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
input B1EN;
EG_LOGIC_DRAM16X4 #(
`include "dram_init_16x4.vh"
`include "lutram_init_16x4.vh"
) _TECHMAP_REPLACE_ (
.di(B1DATA),
.waddr(B1ADDR),

28
techlibs/anlogic/synth_anlogic.cc
View File

@ -58,7 +58,10 @@ struct SynthAnlogicPass : public ScriptPass
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -nolutram\n");
log(" do not use EG_LOGIC_DRAM16X4 cells in output netlist\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -67,7 +70,7 @@ struct SynthAnlogicPass : public ScriptPass
}
string top_opt, edif_file, json_file;
bool flatten, retime;
bool flatten, retime, nolutram;
void clear_flags() YS_OVERRIDE
{
@ -76,6 +79,7 @@ struct SynthAnlogicPass : public ScriptPass
json_file = "";
flatten = true;
retime = false;
nolutram = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@ -110,6 +114,10 @@ struct SynthAnlogicPass : public ScriptPass
flatten = false;
continue;
}
if (args[argidx] == "-nolutram") {
nolutram = true;
continue;
}
if (args[argidx] == "-retime") {
retime = true;
continue;
@ -150,21 +158,25 @@ struct SynthAnlogicPass : public ScriptPass
run("synth -run coarse");
}
if (check_label("dram"))
if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
{
run("memory_bram -rules +/anlogic/drams.txt");
run("techmap -map +/anlogic/drams_map.v");
run("memory_bram -rules +/anlogic/lutrams.txt");
run("techmap -map +/anlogic/lutrams_map.v");
run("setundef -zero -params t:EG_LOGIC_DRAM16X4");
}
if (check_label("fine"))
if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
}
if (check_label("map_gates"))
{
run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
if (retime || help_mode)
run("abc -dff", "(only if -retime)");
run("abc -dff -D 1", "(only if -retime)");
}
if (check_label("map_ffs"))
@ -187,7 +199,7 @@ struct SynthAnlogicPass : public ScriptPass
run("techmap -map +/anlogic/cells_map.v");
run("clean");
}
if (check_label("map_anlogic"))
{
run("anlogic_fixcarry");

4
techlibs/coolrunner2/synth_coolrunner2.cc
View File

@ -55,7 +55,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -161,7 +161,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
if (check_label("map_pla"))
{
run("abc -sop -I 40 -P 56");
run("abc -sop -I 40 -P 56" + string(retime ? " -dff -D 1" : ""));
run("clean");
}

4
techlibs/easic/synth_easic.cc
View File

@ -56,7 +56,7 @@ struct SynthEasicPass : public ScriptPass
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -158,7 +158,7 @@ struct SynthEasicPass : public ScriptPass
run("techmap");
run("opt -fast");
if (retime || help_mode) {
run("abc -dff", " (only if -retime)");
run("abc -dff -D 1", " (only if -retime)");
run("opt_clean", "(only if -retime)");
}
}

4
techlibs/ecp5/Makefile.inc
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@ -8,9 +8,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutram.txt))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams.txt))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams.txt))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))

0
techlibs/ecp5/bram.txt → techlibs/ecp5/brams.txt
View File

0
techlibs/ecp5/lutram.txt → techlibs/ecp5/lutrams.txt
View File

8
techlibs/ecp5/synth_ecp5.cc
View File

@ -62,7 +62,7 @@ struct SynthEcp5Pass : public ScriptPass
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -noccu2\n");
log(" do not use CCU2 cells in output netlist\n");
@ -266,13 +266,13 @@ struct SynthEcp5Pass : public ScriptPass
if (!nobram && check_label("map_bram", "(skip if -nobram)"))
{
run("memory_bram -rules +/ecp5/bram.txt");
run("memory_bram -rules +/ecp5/brams.txt");
run("techmap -map +/ecp5/brams_map.v");
}
if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
{
run("memory_bram -rules +/ecp5/lutram.txt");
run("memory_bram -rules +/ecp5/lutrams.txt");
run("techmap -map +/ecp5/lutrams_map.v");
}
@ -290,7 +290,7 @@ struct SynthEcp5Pass : public ScriptPass
else
run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
if (retime || help_mode)
run("abc -dff", "(only if -retime)");
run("abc -dff -D 1", "(only if -retime)");
}
if (check_label("map_ffs"))

2
techlibs/efinix/Makefile.inc
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@ -7,4 +7,4 @@ $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/bram.txt))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams.txt))

0
techlibs/efinix/bram.txt → techlibs/efinix/brams.txt
View File

26
techlibs/efinix/synth_efinix.cc
View File

@ -58,7 +58,10 @@ struct SynthEfinixPass : public ScriptPass
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -nobram\n");
log(" do not use EFX_RAM_5K cells in output netlist\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -67,7 +70,7 @@ struct SynthEfinixPass : public ScriptPass
}
string top_opt, edif_file, json_file;
bool flatten, retime;
bool flatten, retime, nobram;
void clear_flags() YS_OVERRIDE
{
@ -76,6 +79,7 @@ struct SynthEfinixPass : public ScriptPass
json_file = "";
flatten = true;
retime = false;
nobram = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@ -114,6 +118,10 @@ struct SynthEfinixPass : public ScriptPass
retime = true;
continue;
}
if (args[argidx] == "-nobram") {
nobram = true;
continue;
}
break;
}
extra_args(args, argidx, design);
@ -150,21 +158,25 @@ struct SynthEfinixPass : public ScriptPass
run("synth -run coarse");
}
if (check_label("map_bram", "(skip if -nobram)"))
if (!nobram || check_label("map_bram", "(skip if -nobram)"))
{
run("memory_bram -rules +/efinix/bram.txt");
run("memory_bram -rules +/efinix/brams.txt");
run("techmap -map +/efinix/brams_map.v");
run("setundef -zero -params t:EFX_RAM_5K");
}
if (check_label("fine"))
if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
}
if (check_label("map_gates"))
{
run("techmap -map +/techmap.v -map +/efinix/arith_map.v");
if (retime || help_mode)
run("abc -dff", "(only if -retime)");
run("abc -dff -D 1", "(only if -retime)");
}
if (check_label("map_ffs"))
@ -194,7 +206,7 @@ struct SynthEfinixPass : public ScriptPass
run("efinix_fixcarry");
run("clean");
}
if (check_label("check"))
{
run("hierarchy -check");

6
techlibs/gowin/Makefile.inc
View File

@ -7,9 +7,9 @@ $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/bram.txt))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/drams_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/dram.txt))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt))

0
techlibs/gowin/bram.txt → techlibs/gowin/brams.txt
View File

0
techlibs/gowin/dram.txt → techlibs/gowin/lutrams.txt
View File

0
techlibs/gowin/drams_map.v → techlibs/gowin/lutrams_map.v
View File

53
techlibs/gowin/synth_gowin.cc
View File

@ -55,23 +55,23 @@ struct SynthGowinPass : public ScriptPass
log(" -nobram\n");
log(" do not use BRAM cells in output netlist\n");
log("\n");
log(" -nodram\n");
log(" -nolutram\n");
log(" do not use distributed RAM cells in output netlist\n");
log("\n");
log(" -noflatten\n");
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -nowidelut\n");
log(" do not use muxes to implement LUTs larger than LUT4s\n");
log("\n");
log(" -noiopads\n");
log(" do not emit IOB at top level ports\n");
log("\n");
log(" -abc9\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n");
//log("\n");
//log(" -abc9\n");
//log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -80,7 +80,7 @@ struct SynthGowinPass : public ScriptPass
}
string top_opt, vout_file;
bool retime, nobram, nodram, flatten, nodffe, nowidelut, abc9, noiopads;
bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads;
void clear_flags() YS_OVERRIDE
{
@ -90,7 +90,7 @@ struct SynthGowinPass : public ScriptPass
flatten = true;
nobram = false;
nodffe = false;
nodram = false;
nolutram = false;
nowidelut = false;
abc9 = false;
noiopads = false;
@ -128,8 +128,8 @@ struct SynthGowinPass : public ScriptPass
nobram = true;
continue;
}
if (args[argidx] == "-nodram") {
nodram = true;
if (args[argidx] == "-nolutram" || /*deprecated*/args[argidx] == "-nodram") {
nolutram = true;
continue;
}
if (args[argidx] == "-nodffe") {
@ -144,10 +144,10 @@ struct SynthGowinPass : public ScriptPass
nowidelut = true;
continue;
}
if (args[argidx] == "-abc9") {
abc9 = true;
continue;
}
//if (args[argidx] == "-abc9") {
// abc9 = true;
// continue;
//}
if (args[argidx] == "-noiopads") {
noiopads = true;
continue;
@ -188,28 +188,32 @@ struct SynthGowinPass : public ScriptPass
run("synth -run coarse");
}
if (!nobram && check_label("bram", "(skip if -nobram)"))
if (!nobram && check_label("map_bram", "(skip if -nobram)"))
{
run("memory_bram -rules +/gowin/bram.txt");
run("memory_bram -rules +/gowin/brams.txt");
run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
}
if (!nodram && check_label("dram", "(skip if -nodram)"))
if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
{
run("memory_bram -rules +/gowin/dram.txt");
run("techmap -map +/gowin/drams_map.v");
run("memory_bram -rules +/gowin/lutrams.txt");
run("techmap -map +/gowin/lutrams_map.v");
run("determine_init");
}
if (check_label("fine"))
if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
}
if (check_label("map_gates"))
{
run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
run("techmap -map +/techmap.v");
if (retime || help_mode)
run("abc -dff", "(only if -retime)");
run("abc -dff -D 1", "(only if -retime)");
run("splitnets");
}
@ -227,13 +231,13 @@ struct SynthGowinPass : public ScriptPass
if (check_label("map_luts"))
{
if (nowidelut && abc9) {
/*if (nowidelut && abc9) {
run("abc9 -lut 4");
} else if (nowidelut && !abc9) {
} else*/ if (nowidelut && !abc9) {
run("abc -lut 4");
} else if (!nowidelut && abc9) {
} else /*if (!nowidelut && abc9) {
run("abc9 -lut 4:8");
} else if (!nowidelut && !abc9) {
} else*/ if (!nowidelut && !abc9) {
run("abc -lut 4:8");
}
run("clean");
@ -248,7 +252,6 @@ struct SynthGowinPass : public ScriptPass
run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
"-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)");
run("clean");
}
if (check_label("check"))

4
techlibs/greenpak4/synth_greenpak4.cc
View File

@ -59,7 +59,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -165,7 +165,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
run("opt -fast");
if (retime || help_mode)
run("abc -dff", "(only if -retime)");
run("abc -dff -D 1", "(only if -retime)");
}
if (check_label("map_luts"))

4
techlibs/ice40/synth_ice40.cc
View File

@ -65,7 +65,7 @@ struct SynthIce40Pass : public ScriptPass
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -nocarry\n");
log(" do not use SB_CARRY cells in output netlist\n");
@ -316,7 +316,7 @@ struct SynthIce40Pass : public ScriptPass
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
}
if (retime || help_mode)
run(abc + " -dff", "(only if -retime)");
run(abc + " -dff -D 1", "(only if -retime)");
run("ice40_opt");
}

14
techlibs/intel/synth_intel.cc
View File

@ -71,7 +71,7 @@ struct SynthIntelPass : public ScriptPass {
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
@ -187,10 +187,10 @@ struct SynthIntelPass : public ScriptPass {
}
if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
if (family_opt == "cycloneiv" ||
family_opt == "cycloneive" ||
family_opt == "max10" ||
help_mode) {
if (family_opt == "cycloneiv" ||
family_opt == "cycloneive" ||
family_opt == "max10" ||
help_mode) {
run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)");
run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)");
} else {
@ -210,7 +210,7 @@ struct SynthIntelPass : public ScriptPass {
run("clean -purge");
run("setundef -undriven -zero");
if (retime || help_mode)
run("abc -markgroups -dff", "(only if -retime)");
run("abc -markgroups -dff -D 1", "(only if -retime)");
}
if (check_label("map_luts")) {
@ -224,7 +224,7 @@ struct SynthIntelPass : public ScriptPass {
if (check_label("map_cells")) {
if (iopads || help_mode)
run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(if -iopads)");
run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
run("dffinit -highlow -ff dffeas q power_up");
run("clean -purge");
}

4
techlibs/sf2/synth_sf2.cc
View File

@ -67,7 +67,7 @@ struct SynthSf2Pass : public ScriptPass
log(" insert direct PAD->global_net buffers\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -181,7 +181,7 @@ struct SynthSf2Pass : public ScriptPass
run("opt -undriven -fine");
run("techmap -map +/techmap.v -map +/sf2/arith_map.v");
if (retime || help_mode)
run("abc -dff", "(only if -retime)");
run("abc -dff -D 1", "(only if -retime)");
}
if (check_label("map_ffs"))

12
techlibs/xilinx/cells_sim.v
View File

@ -2244,7 +2244,7 @@ module DSP48E1 (
parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
initial begin
`ifdef __ICARUS__
`ifndef YOSYS
if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value");
if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value");
if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value");
@ -2407,12 +2407,12 @@ module DSP48E1 (
case (OPMODEr[1:0])
2'b00: X = 48'b0;
2'b01: begin X = $signed(Mrx);
`ifdef __ICARUS__
`ifndef YOSYS
if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01");
`endif
end
2'b10: begin X = P;
`ifdef __ICARUS__
`ifndef YOSYS
if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10");
`endif
end
@ -2424,7 +2424,7 @@ module DSP48E1 (
case (OPMODEr[3:2])
2'b00: Y = 48'b0;
2'b01: begin Y = 48'b0; // FIXME: more accurate partial product modelling?
`ifdef __ICARUS__
`ifndef YOSYS
if (OPMODEr[1:0] != 2'b01) $fatal(1, "OPMODEr[1:0] must be 2'b01 when OPMODEr[3:2] is 2'b01");
`endif
end
@ -2438,13 +2438,13 @@ module DSP48E1 (
3'b000: Z = 48'b0;
3'b001: Z = PCIN;
3'b010: begin Z = P;
`ifdef __ICARUS__
`ifndef YOSYS
if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] i0s 3'b010");
`endif
end
3'b011: Z = Cr;
3'b100: begin Z = P;
`ifdef __ICARUS__
`ifndef YOSYS
if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100");
if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100");
`endif

6
techlibs/xilinx/synth_xilinx.cc
View File

@ -111,7 +111,7 @@ struct SynthXilinxPass : public ScriptPass
log(" run 'abc9' with -dff option\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -abc9\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n");
@ -564,9 +564,9 @@ struct SynthXilinxPass : public ScriptPass
}
else {
if (nowidelut)
run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
run("abc -luts 2:2,3,6:5" + string(retime ? " -dff -D 1" : ""));
else
run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff -D 1" : ""));
}
run("clean");

2
tests/arch/anlogic/counter.ys
View File

@ -2,7 +2,7 @@ read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module

2
tests/arch/ecp5/counter.ys
View File

@ -2,7 +2,7 @@ read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
equiv_opt -assert -multiclock -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 4 t:CCU2C

4
tests/arch/ecp5/macc.ys
View File

@ -3,8 +3,8 @@ hierarchy -top top
proc
# Blocked by issue #1358 (Missing ECP5 simulation models)
#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
synth_ecp5
#design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:MULT18X18D
select -assert-count 4 t:CCU2C

4
tests/arch/ecp5/mul.ys
View File

@ -3,9 +3,9 @@ hierarchy -top top
proc
# Blocked by issue #1358 (Missing ECP5 simulation models)
#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
synth_ecp5
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
#design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:MULT18X18D
select -assert-none t:MULT18X18D %% t:* %D

2
tests/arch/efinix/counter.ys
View File

@ -2,7 +2,7 @@ read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
equiv_opt -assert -multiclock -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module

2
tests/arch/gowin/counter.ys
View File

@ -2,7 +2,7 @@ read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
equiv_opt -map +/gowin/cells_sim.v synth_gowin # equivalency check
equiv_opt -assert -multiclock -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module

2
tests/arch/ice40/counter.ys
View File

@ -2,7 +2,7 @@ read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:SB_CARRY

2
tests/arch/ice40/mul.ys
View File

@ -1,6 +1,6 @@
read_verilog ../common/mul.v
hierarchy -top top
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_MAC16

3
tests/arch/ice40/rom.v
View File

@ -2,7 +2,8 @@
Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74].
*/
module top(data, addr);
output [3:0] data;
output [3:0] data; // Note: this prompts a Yosys warning, but
// vendor doc does not contain 'reg'
input [4:0] addr;
always @(addr) begin
case (addr)

19
tests/arch/xilinx/bug1605.ys Normal file
View File

@ -0,0 +1,19 @@
read_verilog <<EOT
module top(inout io);
wire in;
wire t;
wire o;
IOBUF IOBUF(
.I(in),
.T(t),
.IO(io),
.O(o)
);
endmodule
EOT
synth_xilinx
cd top
select -assert-count 1 t:IOBUF
select -assert-none t:* t:IOBUF %d