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clean: ignore specify-s inside cells when determining whether to keep

This commit is contained in:
Eddie Hung 2020-02-19 10:45:10 -08:00
parent d20c1dac73
commit 1d401a7991
2 changed files with 35 additions and 10 deletions
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24
passes/opt/opt_clean.cc
View File

@ -51,20 +51,26 @@ struct keep_cache_t
if (cache.count(module))
return cache.at(module);
cache[module] = true;
if (!module->get_bool_attribute(ID::keep)) {
bool found_keep = false;
bool found_keep = false;
if (module->get_bool_attribute(ID::keep))
found_keep = true;
else
for (auto cell : module->cells())
if (query(cell)) found_keep = true;
cache[module] = found_keep;
}
if (query(cell, true /* ignore_specify */)) {
found_keep = true;
break;
}
cache[module] = found_keep;
return cache[module];
return found_keep;
}
bool query(Cell *cell)
bool query(Cell *cell, bool ignore_specify = false)
{
if (cell->type.in(ID($memwr), ID($meminit), ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($specify2), ID($specify3), ID($specrule)))
if (cell->type.in(ID($memwr), ID($meminit), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
return true;
if (!ignore_specify && cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
return true;
if (cell->has_keep_attr())

21
tests/various/specify.ys
View File

@ -55,4 +55,23 @@ equiv_induct -seq 5
equiv_status -assert
design -reset
read_verilog specify.v
read_verilog -specify <<EOT
(* blackbox *)
module test7_sub(input i, output o);
specify
(i => o) = 1;
endspecify
assign o = ~i;
endmodule
module test7(input i, output o);
wire w;
test7_sub unused(i, w);
test7_sub used(i, o);
endmodule
EOT
hierarchy
cd test7
clean
select -assert-count 1 c:used
select -assert-none c:* c:used %d