mirror of https://github.com/YosysHQ/yosys.git
abc9: -reintegrate recover type from existing cell, check against boxid
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@ -356,24 +356,14 @@ void reintegrate(RTLIL::Module *module)
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for (auto w : mapped_mod->wires())
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module->addWire(remap_name(w->name), GetSize(w));
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dict<IdString,IdString> box_lookup;
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dict<IdString,std::vector<IdString>> box_ports;
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for (auto m : design->modules()) {
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auto it = m->attributes.find(ID(abc9_box_id));
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if (it == m->attributes.end())
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if (!m->attributes.count(ID(abc9_box_id)))
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continue;
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if (m->name.begins_with("$paramod"))
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continue;
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auto id = it->second.as_int();
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auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
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if (!r.second)
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log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
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log_id(m), id, log_id(r.first->second));
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log_assert(r.second);
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auto r2 = box_ports.insert(m->name);
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if (r2.second) {
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auto r = box_ports.insert(m->name);
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if (r.second) {
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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@ -393,7 +383,7 @@ void reintegrate(RTLIL::Module *module)
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}
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}
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else
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r2.first->second.push_back(port_name);
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r.first->second.push_back(port_name);
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}
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if (carry_in != IdString() && carry_out == IdString())
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@ -401,8 +391,8 @@ void reintegrate(RTLIL::Module *module)
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
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if (carry_in != IdString()) {
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r2.first->second.push_back(carry_in);
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r2.first->second.push_back(carry_out);
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r.first->second.push_back(carry_in);
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r.first->second.push_back(carry_out);
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}
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}
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}
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@ -516,28 +506,27 @@ void reintegrate(RTLIL::Module *module)
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else {
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RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
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log_assert(existing_cell);
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log_assert(mapped_cell->type.begins_with("$__boxid"));
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auto type = box_lookup.at(mapped_cell->type, IdString());
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if (type == IdString())
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log_error("No module with abc9_box_id = %s found.\n", mapped_cell->type.c_str() + strlen("$__boxid"));
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mapped_cell->type = type;
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RTLIL::Module* box_module = design->module(existing_cell->type);
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auto it = box_module->attributes.find(ID(abc9_box_id));
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log_assert(it != box_module->attributes.end());
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log_assert(mapped_cell->type == stringf("$__boxid%d", it->second.as_int()));
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mapped_cell->type = existing_cell->type;
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RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
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cell->parameters = existing_cell->parameters;
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cell->attributes = existing_cell->attributes;
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module->swap_names(cell, existing_cell);
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auto it = mapped_cell->connections_.find("\\i");
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log_assert(it != mapped_cell->connections_.end());
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SigSpec inputs = std::move(it->second);
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mapped_cell->connections_.erase(it);
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it = mapped_cell->connections_.find("\\o");
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log_assert(it != mapped_cell->connections_.end());
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SigSpec outputs = std::move(it->second);
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mapped_cell->connections_.erase(it);
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auto jt = mapped_cell->connections_.find("\\i");
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log_assert(jt != mapped_cell->connections_.end());
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SigSpec inputs = std::move(jt->second);
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mapped_cell->connections_.erase(jt);
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jt = mapped_cell->connections_.find("\\o");
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log_assert(jt != mapped_cell->connections_.end());
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SigSpec outputs = std::move(jt->second);
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mapped_cell->connections_.erase(jt);
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RTLIL::Module* box_module = design->module(mapped_cell->type);
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auto abc9_flop = box_module->attributes.count("\\abc9_flop");
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if (!abc9_flop) {
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for (const auto &i : inputs)
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