mirror of https://github.com/YosysHQ/yosys.git
opt_merge: speedup
This commit is contained in:
Eddie Hung
parent
a0cc795e85
commit
9f30d7f843
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@ -26,7 +26,6 @@
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#include <stdio.h>
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#include <set>
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#define USE_CELL_HASH_CACHE
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -41,9 +40,7 @@ struct OptMergeWorker
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CellTypes ct;
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int total_count;
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#ifdef USE_CELL_HASH_CACHE
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dict<const RTLIL::Cell*, std::string> cell_hash_cache;
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#endif
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SHA1 checksum;
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static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
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{
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@ -68,7 +65,6 @@ struct OptMergeWorker
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}
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}
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#ifdef USE_CELL_HASH_CACHE
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std::string int_to_hash_string(unsigned int v)
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{
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if (v == 0)
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@ -83,14 +79,9 @@ struct OptMergeWorker
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std::string hash_cell_parameters_and_connections(const RTLIL::Cell *cell)
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{
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if (cell_hash_cache.count(cell) > 0)
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return cell_hash_cache[cell];
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vector<string> hash_conn_strings;
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std::string hash_string = cell->type.str() + "\n";
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for (auto &it : cell->parameters)
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hash_string += "P " + it.first.str() + "=" + it.second.as_string() + "\n";
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const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
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dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
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@ -124,13 +115,22 @@ struct OptMergeWorker
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conn = &alt_conn;
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}
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vector<string> hash_conn_strings;
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for (auto &it : *conn) {
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if (cell->output(it.first))
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continue;
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RTLIL::SigSpec sig = it.second;
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assign_map.apply(sig);
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RTLIL::SigSpec sig;
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if (cell->output(it.first)) {
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if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
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cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
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cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
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// For the 'Q' output of state elements,
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// use its (* init *) attribute value
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for (const auto &b : dff_init_map(it.second))
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sig.append(b.wire ? State::Sx : b);
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}
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else
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continue;
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}
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else
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sig = assign_map(it.second);
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string s = "C " + it.first.str() + "=";
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for (auto &chunk : sig.chunks()) {
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if (chunk.wire)
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@ -143,50 +143,59 @@ struct OptMergeWorker
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hash_conn_strings.push_back(s + "\n");
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}
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for (auto &it : cell->parameters)
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hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n");
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std::sort(hash_conn_strings.begin(), hash_conn_strings.end());
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for (auto it : hash_conn_strings)
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hash_string += it;
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cell_hash_cache[cell] = sha1(hash_string);
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return cell_hash_cache[cell];
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checksum.update(hash_string);
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return checksum.final();
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}
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#endif
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bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2, bool <)
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bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
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{
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#ifdef USE_CELL_HASH_CACHE
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std::string hash1 = hash_cell_parameters_and_connections(cell1);
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std::string hash2 = hash_cell_parameters_and_connections(cell2);
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log_assert(cell1 != cell2);
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if (cell1->type != cell2->type) return false;
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if (hash1 != hash2) {
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lt = hash1 < hash2;
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return true;
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}
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#endif
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if (cell1->parameters != cell2->parameters)
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return false;
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if (cell1->parameters != cell2->parameters) {
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std::map<RTLIL::IdString, RTLIL::Const> p1(cell1->parameters.begin(), cell1->parameters.end());
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std::map<RTLIL::IdString, RTLIL::Const> p2(cell2->parameters.begin(), cell2->parameters.end());
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lt = p1 < p2;
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return true;
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}
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if (cell1->connections_.size() != cell2->connections_.size())
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return false;
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for (const auto &it : cell1->connections_)
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if (!cell2->connections_.count(it.first))
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return false;
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dict<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections();
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dict<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections();
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decltype(Cell::connections_) conn1, conn2;
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conn1.reserve(cell1->connections_.size());
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conn2.reserve(cell1->connections_.size());
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for (auto &it : conn1) {
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if (cell1->output(it.first))
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it.second = RTLIL::SigSpec();
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else
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assign_map.apply(it.second);
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}
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for (auto &it : conn2) {
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if (cell2->output(it.first))
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it.second = RTLIL::SigSpec();
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else
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assign_map.apply(it.second);
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for (const auto &it : cell1->connections_) {
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if (cell1->output(it.first)) {
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if (it.first == ID(Q) && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
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cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
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cell1->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
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// For the 'Q' output of state elements,
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// use the (* init *) attribute value
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auto &sig1 = conn1[it.first];
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for (const auto &b : dff_init_map(it.second))
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sig1.append(b.wire ? State::Sx : b);
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auto &sig2 = conn2[it.first];
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for (const auto &b : dff_init_map(cell2->getPort(it.first)))
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sig2.append(b.wire ? State::Sx : b);
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}
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else {
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conn1[it.first] = RTLIL::SigSpec();
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conn2[it.first] = RTLIL::SigSpec();
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}
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}
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else {
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conn1[it.first] = assign_map(it.second);
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conn2[it.first] = assign_map(cell2->getPort(it.first));
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}
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}
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if (cell1->type == ID($and) || cell1->type == ID($or) || cell1->type == ID($xor) || cell1->type == ID($xnor) || cell1->type == ID($add) || cell1->type == ID($mul) ||
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@ -215,54 +224,9 @@ struct OptMergeWorker
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sort_pmux_conn(conn2);
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}
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if (conn1 != conn2) {
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std::map<RTLIL::IdString, RTLIL::SigSpec> c1(conn1.begin(), conn1.end());
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std::map<RTLIL::IdString, RTLIL::SigSpec> c2(conn2.begin(), conn2.end());
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lt = c1 < c2;
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return true;
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}
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if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
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cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
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cell1->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
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std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector();
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std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector();
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for (size_t i = 0; i < q1.size(); i++)
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if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) {
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lt = q1.at(i) < q2.at(i);
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return true;
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}
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}
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return false;
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return conn1 == conn2;
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}
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bool compare_cells(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
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{
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if (cell1->type != cell2->type)
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return cell1->type < cell2->type;
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if ((!mode_share_all && !ct.cell_known(cell1->type)) || !cell1->known())
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return cell1 < cell2;
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if (cell1->has_keep_attr() || cell2->has_keep_attr())
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return cell1 < cell2;
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bool lt;
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if (compare_cell_parameters_and_connections(cell1, cell2, lt))
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return lt;
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return false;
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}
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struct CompareCells {
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OptMergeWorker *that;
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CompareCells(OptMergeWorker *that) : that(that) {}
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bool operator()(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) const {
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return that->compare_cells(cell1, cell2);
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}
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};
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OptMergeWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all) :
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design(design), module(module), assign_map(module), mode_share_all(mode_share_all)
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{
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@ -299,9 +263,6 @@ struct OptMergeWorker
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bool did_something = true;
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while (did_something)
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{
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#ifdef USE_CELL_HASH_CACHE
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cell_hash_cache.clear();
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#endif
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std::vector<RTLIL::Cell*> cells;
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cells.reserve(module->cells_.size());
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for (auto &it : module->cells_) {
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@ -312,42 +273,51 @@ struct OptMergeWorker
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}
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did_something = false;
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std::map<RTLIL::Cell*, RTLIL::Cell*, CompareCells> sharemap(CompareCells(this));
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std::unordered_map<std::string, RTLIL::Cell*> sharemap;
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for (auto cell : cells)
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{
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if (sharemap.count(cell) > 0) {
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did_something = true;
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log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
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for (auto &it : cell->connections()) {
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if (cell->output(it.first)) {
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RTLIL::SigSpec other_sig = sharemap[cell]->getPort(it.first);
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log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
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log_signal(it.second), log_signal(other_sig));
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module->connect(RTLIL::SigSig(it.second, other_sig));
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assign_map.add(it.second, other_sig);
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if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known())
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continue;
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if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
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cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
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cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
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for (auto c : it.second.chunks()) {
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auto jt = c.wire->attributes.find(ID(init));
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if (jt == c.wire->attributes.end())
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continue;
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for (int i = c.offset; i < c.offset + c.width; i++)
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jt->second[i] = State::Sx;
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auto hash = hash_cell_parameters_and_connections(cell);
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auto r = sharemap.insert(std::make_pair(hash, cell));
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if (!r.second) {
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if (compare_cell_parameters_and_connections(cell, r.first->second)) {
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if (cell->has_keep_attr()) {
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if (r.first->second->has_keep_attr())
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continue;
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std::swap(r.first->second, cell);
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}
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did_something = true;
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log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), r.first->second->name.c_str());
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for (auto &it : cell->connections()) {
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if (cell->output(it.first)) {
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RTLIL::SigSpec other_sig = r.first->second->getPort(it.first);
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log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
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log_signal(it.second), log_signal(other_sig));
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module->connect(RTLIL::SigSig(it.second, other_sig));
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assign_map.add(it.second, other_sig);
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if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
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cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
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cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
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for (auto c : it.second.chunks()) {
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auto jt = c.wire->attributes.find(ID(init));
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if (jt == c.wire->attributes.end())
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continue;
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for (int i = c.offset; i < c.offset + c.width; i++)
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jt->second[i] = State::Sx;
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}
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dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second)));
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}
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dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second)));
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}
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}
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log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
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module->remove(cell);
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total_count++;
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}
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log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
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#ifdef USE_CELL_HASH_CACHE
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cell_hash_cache.erase(cell);
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#endif
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module->remove(cell);
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total_count++;
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} else {
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sharemap[cell] = cell;
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}
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}
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}
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@ -20,6 +20,7 @@ endmodule
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EOT
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opt_merge
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select -assert-count 1 t:$dff
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select -assert-count 1 a:init=1'0
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@ -46,4 +47,31 @@ endmodule
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EOT
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opt_merge
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select -assert-count 1 t:$dff
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select -assert-count 1 a:init=2'bx1
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design -reset
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read_verilog -icells <<EOT
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module top(input clk, i, (* init = 1'b0 *) output o, /* NB: no init here! */ output p);
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\$dff #(
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.CLK_POLARITY(1'h1),
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.WIDTH(32'd1)
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) ffo (
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.CLK(clk),
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.D(i),
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.Q(o)
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);
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\$dff #(
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.CLK_POLARITY(1'h1),
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.WIDTH(32'd1)
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) ffp (
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.CLK(clk),
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.D(i),
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.Q(p)
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);
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endmodule
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EOT
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opt_merge
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select -assert-count 2 t:$dff
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@ -0,0 +1,64 @@
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read_verilog -icells <<EOT
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module top(input clk, i, output o, p);
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(* keep *)
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\$_DFF_P_ ffo (
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.C(clk),
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.D(i),
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.Q(o)
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);
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\$_DFF_P_ ffp (
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.C(clk),
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.D(i),
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.Q(p)
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);
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endmodule
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EOT
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opt_merge
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select -assert-count 1 t:$_DFF_P_
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select -assert-count 1 a:keep
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design -reset
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read_verilog -icells <<EOT
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module top(input clk, i, output o, p);
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\$_DFF_P_ ffo (
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.C(clk),
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.D(i),
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.Q(o)
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);
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(* keep *)
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\$_DFF_P_ ffp (
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.C(clk),
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.D(i),
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.Q(p)
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);
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endmodule
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EOT
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opt_merge
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select -assert-count 1 t:$_DFF_P_
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select -assert-count 1 a:keep
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design -reset
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read_verilog -icells <<EOT
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module top(input clk, i, output o, p);
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(* keep *)
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\$_DFF_P_ ffo (
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.C(clk),
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.D(i),
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.Q(o)
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);
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(* keep *)
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\$_DFF_P_ ffp (
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.C(clk),
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.D(i),
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.Q(p)
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);
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endmodule
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EOT
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opt_merge
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select -assert-count 2 t:$_DFF_P_
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select -assert-count 2 a:keep
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