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Merge pull request #2153 from boqwxp/splitnets-cleanup 

splitnets: Cleanup and efficiency improvements
This commit is contained in:
N. Engelhardt 2020-06-18 19:16:55 +02:00 committed by GitHub
parent 8344846787 f5d7cd60f5
commit dfde1cf1c5
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 19 additions and 16 deletions
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35
passes/cmds/splitnets.cc
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@ -61,20 +61,24 @@ struct SplitnetsWorker
new_wire->port_output = wire->port_output;
new_wire->start_offset = wire->start_offset + offset;
if (wire->attributes.count(ID::src))
new_wire->attributes[ID::src] = wire->attributes.at(ID::src);
auto it = wire->attributes.find(ID::src);
if (it != wire->attributes.end())
new_wire->attributes.emplace(ID::src, it->second);
if (wire->attributes.count(ID::hdlname))
new_wire->attributes[ID::hdlname] = wire->attributes.at(ID::hdlname);
it = wire->attributes.find(ID::hdlname);
if (it != wire->attributes.end())
new_wire->attributes.emplace(ID::hdlname, it->second);
if (wire->attributes.count(ID::keep))
new_wire->attributes[ID::keep] = wire->attributes.at(ID::keep);
it = wire->attributes.find(ID::keep);
if (it != wire->attributes.end())
new_wire->attributes.emplace(ID::keep, it->second);
if (wire->attributes.count(ID::init)) {
Const old_init = wire->attributes.at(ID::init), new_init;
it = wire->attributes.find(ID::init);
if (it != wire->attributes.end()) {
Const old_init = it->second, new_init;
for (int i = offset; i < offset+width; i++)
new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx);
new_wire->attributes[ID::init] = new_init;
new_wire->attributes.emplace(ID::init, new_init);
}
std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();
@ -170,12 +174,12 @@ struct SplitnetsPass : public Pass {
std::map<RTLIL::Wire*, std::set<int>> split_wires_at;
for (auto &c : module->cells_)
for (auto &p : c.second->connections())
for (auto c : module->cells())
for (auto &p : c->connections())
{
if (!ct.cell_known(c.second->type))
if (!ct.cell_known(c->type))
continue;
if (!ct.cell_output(c.second->type, p.first))
if (!ct.cell_output(c->type, p.first))
continue;
RTLIL::SigSpec sig = p.second;
@ -202,9 +206,8 @@ struct SplitnetsPass : public Pass {
}
else
{
for (auto &w : module->wires_) {
RTLIL::Wire *wire = w.second;
if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second))
for (auto wire : module->wires()) {
if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, wire))
worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
}