mirror of https://github.com/YosysHQ/yosys.git
splitnets: Clean up pseudo-private member usage
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@ -174,12 +174,12 @@ struct SplitnetsPass : public Pass {
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std::map<RTLIL::Wire*, std::set<int>> split_wires_at;
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for (auto &c : module->cells_)
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for (auto &p : c.second->connections())
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for (auto c : module->cells())
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for (auto &p : c->connections())
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{
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if (!ct.cell_known(c.second->type))
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if (!ct.cell_known(c->type))
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continue;
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if (!ct.cell_output(c.second->type, p.first))
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if (!ct.cell_output(c->type, p.first))
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continue;
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RTLIL::SigSpec sig = p.second;
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@ -206,9 +206,8 @@ struct SplitnetsPass : public Pass {
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}
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else
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{
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for (auto &w : module->wires_) {
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RTLIL::Wire *wire = w.second;
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if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second))
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for (auto wire : module->wires()) {
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if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, wire))
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worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
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}
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