mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #2168 from whitequark/assert-unused-exprs
Use (and ignore) the expression provided to log_assert in NDEBUG builds
This commit is contained in:
clairexen
GitHub
commit
c7d71f436d
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@ -362,9 +362,7 @@ void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
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void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
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{
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#ifndef NDEBUG
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int init_autoidx = autoidx;
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#endif
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if (!flag_m) {
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int count_selected_mods = 0;
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@ -69,7 +69,7 @@ struct ConstEvalAig
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continue;
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for (auto &it2 : it.second->connections())
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if (yosys_celltypes.cell_output(it.second->type, it2.first)) {
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auto r YS_ATTRIBUTE(unused) = sig2driver.insert(std::make_pair(it2.second, it.second));
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auto r = sig2driver.insert(std::make_pair(it2.second, it.second));
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log_assert(r.second);
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}
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}
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@ -400,9 +400,9 @@ void AigerReader::parse_xaiger()
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for (int c = f.get(); c != EOF; c = f.get()) {
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// XAIGER extensions
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if (c == 'm') {
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uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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uint32_t dataSize = parse_xaiger_literal(f);
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uint32_t lutNum = parse_xaiger_literal(f);
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uint32_t lutSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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uint32_t lutSize = parse_xaiger_literal(f);
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log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
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ConstEvalAig ce(module);
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for (unsigned i = 0; i < lutNum; ++i) {
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@ -434,7 +434,7 @@ void AigerReader::parse_xaiger()
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int gray = j ^ (j >> 1);
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ce.set_incremental(input_sig, RTLIL::Const{gray, GetSize(input_sig)});
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RTLIL::SigBit o(output_sig);
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bool success YS_ATTRIBUTE(unused) = ce.eval(o);
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bool success = ce.eval(o);
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log_assert(success);
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log_assert(o.wire == nullptr);
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lut_mask[gray] = o.data;
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@ -446,7 +446,7 @@ void AigerReader::parse_xaiger()
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}
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}
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else if (c == 'r') {
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uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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uint32_t dataSize = parse_xaiger_literal(f);
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flopNum = parse_xaiger_literal(f);
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log_debug("flopNum = %u\n", flopNum);
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log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
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@ -455,7 +455,7 @@ void AigerReader::parse_xaiger()
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mergeability.emplace_back(parse_xaiger_literal(f));
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}
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else if (c == 's') {
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uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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uint32_t dataSize = parse_xaiger_literal(f);
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flopNum = parse_xaiger_literal(f);
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log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
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initial_state.reserve(flopNum);
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@ -469,15 +469,15 @@ void AigerReader::parse_xaiger()
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}
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else if (c == 'h') {
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f.ignore(sizeof(uint32_t));
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uint32_t version YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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uint32_t version = parse_xaiger_literal(f);
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log_assert(version == 1);
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uint32_t ciNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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uint32_t ciNum = parse_xaiger_literal(f);
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log_debug("ciNum = %u\n", ciNum);
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uint32_t coNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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uint32_t coNum = parse_xaiger_literal(f);
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log_debug("coNum = %u\n", coNum);
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piNum = parse_xaiger_literal(f);
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log_debug("piNum = %u\n", piNum);
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uint32_t poNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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uint32_t poNum = parse_xaiger_literal(f);
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log_debug("poNum = %u\n", poNum);
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uint32_t boxNum = parse_xaiger_literal(f);
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log_debug("boxNum = %u\n", boxNum);
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@ -778,7 +778,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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while (node->simplify(true, false, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM))
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did_something = true;
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if (node->type == AST_ENUM) {
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for (auto enode YS_ATTRIBUTE(unused) : node->children){
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for (auto enode : node->children){
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log_assert(enode->type==AST_ENUM_ITEM);
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while (node->simplify(true, false, false, 1, -1, false, in_param))
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did_something = true;
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@ -1886,7 +1886,7 @@ struct VerificExtNets
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new_net = new Net(name.c_str());
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nl->Add(new_net);
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Net *n YS_ATTRIBUTE(unused) = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
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Net *n = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
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log_assert(n == ca_net);
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}
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@ -157,11 +157,10 @@ void log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1
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#ifndef NDEBUG
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static inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; }
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# define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)
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#else
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static inline bool ys_debug(int = 0) { return false; }
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# define log_debug(_fmt, ...) do { } while (0)
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#endif
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# define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)
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static inline void log_suppressed() {
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if (log_debug_suppressed && !log_make_debug) {
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@ -236,7 +235,7 @@ static inline void log_assert_worker(bool cond, const char *expr, const char *fi
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}
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# define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)
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#else
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# define log_assert(_assert_expr_)
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# define log_assert(_assert_expr_) do { if (0) { (void)(_assert_expr_); } } while(0)
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#endif
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#define log_abort() YOSYS_NAMESPACE_PREFIX log_error("Abort in %s:%d.\n", __FILE__, __LINE__)
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@ -369,7 +368,7 @@ static inline void log_dump_val_worker(char *v) { log("%s", v); }
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static inline void log_dump_val_worker(const char *v) { log("%s", v); }
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static inline void log_dump_val_worker(std::string v) { log("%s", v.c_str()); }
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static inline void log_dump_val_worker(PerformanceTimer p) { log("%f seconds", p.sec()); }
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static inline void log_dump_args_worker(const char *p YS_ATTRIBUTE(unused)) { log_assert(*p == 0); }
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static inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }
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void log_dump_val_worker(RTLIL::IdString v);
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void log_dump_val_worker(RTLIL::SigSpec v);
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void log_dump_val_worker(RTLIL::State v);
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@ -107,10 +107,8 @@ struct Macc
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std::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits;
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int config_cursor = 0;
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#ifndef NDEBUG
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int config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();
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log_assert(GetSize(config_bits) >= config_width);
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#endif
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int num_bits = 0;
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if (config_bits[config_cursor++] == State::S1) num_bits |= 1;
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@ -169,7 +169,7 @@ struct ModIndex : public RTLIL::Monitor
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port_add(cell, port, sig);
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}
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void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) override
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void notify_connect(RTLIL::Module *mod, const RTLIL::SigSig &sigsig) override
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{
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log_assert(module == mod);
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@ -214,13 +214,13 @@ struct ModIndex : public RTLIL::Monitor
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}
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}
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void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) override
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void notify_connect(RTLIL::Module *mod, const std::vector<RTLIL::SigSig>&) override
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{
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log_assert(module == mod);
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auto_reload_module = true;
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}
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void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) override
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void notify_blackout(RTLIL::Module *mod) override
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{
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log_assert(module == mod);
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auto_reload_module = true;
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@ -144,6 +144,14 @@ extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *p
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# define YS_ATTRIBUTE(...)
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#endif
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#if __cplusplus >= 201703L
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# define YS_MAYBE_UNUSED [[maybe_unused]];
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#elif defined(__GNUC__) || defined(__clang__)
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# define YS_MAYBE_UNUSED __attribute__((__unused__))
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#else
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# define YS_MAYBE_UNUSED
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#endif
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#if __cplusplus >= 201703L
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# define YS_FALLTHROUGH [[fallthrough]];
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#elif defined(__clang__)
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@ -117,7 +117,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
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}
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void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell,
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const std::string &info YS_ATTRIBUTE(unused), IdString out_port, RTLIL::SigSpec out_val)
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const std::string &info, IdString out_port, RTLIL::SigSpec out_val)
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{
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RTLIL::SigSpec Y = cell->getPort(out_port);
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out_val.extend_u0(Y.size(), false);
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@ -589,7 +589,7 @@ with open(outfile, "w") as f:
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if block["type"] in ("match", "code"):
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print(" // {}".format(block["src"]), file=f)
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print(" void block_{}(int recursion YS_ATTRIBUTE(unused)) {{".format(index), file=f)
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print(" void block_{}(int recursion YS_MAYBE_UNUSED) {{".format(index), file=f)
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current_pattern, current_subpattern = block["pattern"]
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if block["type"] == "final":
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@ -636,17 +636,17 @@ with open(outfile, "w") as f:
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for s in sorted(const_st):
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t = state_types[current_pattern][s]
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if t.endswith("*"):
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print(" {} const &{} YS_ATTRIBUTE(unused) = st_{}.{};".format(t, s, current_pattern, s), file=f)
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print(" {} const &{} YS_MAYBE_UNUSED = st_{}.{};".format(t, s, current_pattern, s), file=f)
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else:
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print(" const {} &{} YS_ATTRIBUTE(unused) = st_{}.{};".format(t, s, current_pattern, s), file=f)
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print(" const {} &{} YS_MAYBE_UNUSED = st_{}.{};".format(t, s, current_pattern, s), file=f)
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for s in sorted(nonconst_st):
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t = state_types[current_pattern][s]
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print(" {} &{} YS_ATTRIBUTE(unused) = st_{}.{};".format(t, s, current_pattern, s), file=f)
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print(" {} &{} YS_MAYBE_UNUSED = st_{}.{};".format(t, s, current_pattern, s), file=f)
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for u in sorted(udata_types[current_pattern].keys()):
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t = udata_types[current_pattern][u]
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print(" {} &{} YS_ATTRIBUTE(unused) = ud_{}.{};".format(t, u, current_pattern, u), file=f)
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print(" {} &{} YS_MAYBE_UNUSED = ud_{}.{};".format(t, u, current_pattern, u), file=f)
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if len(restore_st):
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print("", file=f)
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@ -676,7 +676,7 @@ with open(outfile, "w") as f:
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print("", file=f)
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print("rollback_label:", file=f)
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print(" YS_ATTRIBUTE(unused);", file=f)
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print(" YS_MAYBE_UNUSED;", file=f)
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if len(block["fcode"]):
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print("#define accept do { accept_cnt++; on_accept(); } while(0)", file=f)
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@ -684,7 +684,7 @@ with open(outfile, "w") as f:
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for line in block["fcode"]:
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print(" " + line, file=f)
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print("finish_label:", file=f)
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print(" YS_ATTRIBUTE(unused);", file=f)
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print(" YS_MAYBE_UNUSED;", file=f)
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print("#undef accept", file=f)
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print("#undef finish", file=f)
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@ -733,13 +733,13 @@ with open(outfile, "w") as f:
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valueidx = 1
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for item in block["setup"]:
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if item[0] == "slice":
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print(" const int &{} YS_ATTRIBUTE(unused) = std::get<{}>(cells[_pmg_idx]);".format(item[1], valueidx), file=f)
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print(" const int &{} YS_MAYBE_UNUSED = std::get<{}>(cells[_pmg_idx]);".format(item[1], valueidx), file=f)
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valueidx += 1
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if item[0] == "choice":
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print(" const {} &{} YS_ATTRIBUTE(unused) = std::get<{}>(cells[_pmg_idx]);".format(item[1], item[2], valueidx), file=f)
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print(" const {} &{} YS_MAYBE_UNUSED = std::get<{}>(cells[_pmg_idx]);".format(item[1], item[2], valueidx), file=f)
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valueidx += 1
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if item[0] == "define":
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print(" const {} &{} YS_ATTRIBUTE(unused) = std::get<{}>(cells[_pmg_idx]);".format(item[1], item[2], valueidx), file=f)
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print(" const {} &{} YS_MAYBE_UNUSED = std::get<{}>(cells[_pmg_idx]);".format(item[1], item[2], valueidx), file=f)
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valueidx += 1
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print(" if (blacklist_cells.count({})) continue;".format(block["cell"]), file=f)
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for expr in block["filter"]:
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@ -741,7 +741,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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if (ys_debug(1))
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toposort.analyze_loops = true;
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bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
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bool no_loops = toposort.sort();
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if (ys_debug(1)) {
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unsigned i = 0;
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@ -1453,7 +1453,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
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for (auto driver_cell : bit_drivers.at(it.first))
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
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bool no_loops = toposort.sort();
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log_assert(no_loops);
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for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
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@ -409,11 +409,11 @@ static void map_sr_to_arst(IdString from, IdString to)
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if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
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return;
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char from_clk_pol YS_ATTRIBUTE(unused) = from[8];
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char from_clk_pol = from[8];
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char from_set_pol = from[9];
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char from_clr_pol = from[10];
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char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
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char to_rst_pol YS_ATTRIBUTE(unused) = to[7];
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char to_clk_pol = to[6];
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char to_rst_pol = to[7];
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char to_rst_val = to[8];
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log_assert(from_clk_pol == to_clk_pol);
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@ -455,9 +455,9 @@ static void map_adff_to_dff(IdString from, IdString to)
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if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
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return;
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char from_clk_pol YS_ATTRIBUTE(unused) = from[6];
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char from_clk_pol = from[6];
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char from_rst_pol = from[7];
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char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
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char to_clk_pol = to[6];
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log_assert(from_clk_pol == to_clk_pol);
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@ -132,7 +132,7 @@ static void test_abcloop()
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SatGen satgen(ez.get(), &sigmap);
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for (auto c : module->cells()) {
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bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
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bool ok = satgen.importCell(c);
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log_assert(ok);
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}
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@ -182,7 +182,7 @@ static void test_abcloop()
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SatGen satgen(ez.get(), &sigmap);
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for (auto c : module->cells()) {
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bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
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bool ok = satgen.importCell(c);
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log_assert(ok);
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}
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