mirror of https://github.com/YosysHQ/yosys.git
abc9_ops: fix bypass boxes using (* abc9_bypass *)
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parent
d5a8aaba8c
commit
b3e2538a14
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@ -2,10 +2,9 @@ X(A)
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X(abc9_box)
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X(abc9_box_id)
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X(abc9_box_seq)
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X(abc9_bypass)
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X(abc9_carry)
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X(abc9_flop)
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X(abc9_holes)
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X(abc9_init)
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X(abc9_lut)
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X(abc9_mergeability)
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X(abc9_scc)
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@ -102,7 +102,7 @@ void check(RTLIL::Design *design, bool dff_mode)
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auto inst_module = design->module(cell->type);
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if (!inst_module)
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continue;
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if (!inst_module->attributes.count(ID::abc9_flop))
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if (!inst_module->get_bool_attribute(ID::abc9_flop))
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continue;
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auto derived_type = inst_module->derive(design, cell->parameters);
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if (!processed.insert(derived_type).second)
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@ -171,9 +171,9 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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if (derived_module->get_blackbox_attribute(true /* ignore_wb */))
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continue;
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if (inst_module->attributes.count(ID::abc9_flop) && !dff_mode)
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if (inst_module->get_bool_attribute(ID::abc9_flop) && !dff_mode)
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continue;
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if (!inst_module->attributes.count(ID::abc9_box) && !inst_module->attributes.count(ID::abc9_flop))
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if (!inst_module->get_bool_attribute(ID::abc9_box) && !inst_module->get_bool_attribute(ID::abc9_flop))
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continue;
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if (!unmap_design->module(derived_type)) {
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@ -205,13 +205,11 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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break;
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}
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if (!found) {
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derived_module->set_bool_attribute(ID::abc9_box, false);
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log_assert(!derived_module->attributes.count(ID::abc9_box));
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if (!found)
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goto skip_cell;
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}
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derived_module->set_bool_attribute(ID::abc9_box, false);
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derived_module->set_bool_attribute(ID::abc9_bypass);
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}
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if (derived_type != cell->type) {
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@ -265,9 +263,8 @@ void prep_bypass(RTLIL::Design *design)
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auto derived_type = inst_module->derive(design, cell->parameters);
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inst_module = design->module(derived_type);
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log_assert(inst_module);
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if (inst_module->get_blackbox_attribute(true /* ignore_wb */))
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continue;
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if (!inst_module->get_bool_attribute(ID::abc9_box))
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log_assert(!inst_module->get_blackbox_attribute(true /* ignore_wb */));
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if (!inst_module->get_bool_attribute(ID::abc9_bypass))
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continue;
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@ -444,7 +441,7 @@ void prep_dff(RTLIL::Design *design)
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auto inst_module = design->module(cell->type);
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if (!inst_module)
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continue;
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if (!inst_module->attributes.count(ID::abc9_flop))
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if (!inst_module->get_bool_attribute(ID::abc9_flop))
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continue;
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auto derived_type = inst_module->derive(design, cell->parameters);
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auto derived_module = design->module(derived_type);
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@ -589,7 +586,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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continue;
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auto inst_module = design->module(cell->type);
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bool abc9_flop = inst_module && inst_module->attributes.count(ID::abc9_flop);
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bool abc9_flop = inst_module && inst_module->get_bool_attribute(ID::abc9_flop);
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if (abc9_flop && !dff)
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continue;
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