riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Do not modify design modules while iterating over `modules()`. 

Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
This commit is contained in:
Alberto Gonzalez 2020-04-10 07:19:05 +00:00
parent 985a29ff3b
commit e49fdee404
No known key found for this signature in database
GPG Key ID: 8395A8BA109708B2
1 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
passes/techmap/techmap.cc
View File

@ -1423,11 +1423,14 @@ struct FlattenPass : public Pass {
new_used_modules.insert(cell->type);
}
std::set<RTLIL::Module *> to_remove;
for (auto mod : design->modules())
if (!used_modules[mod->name] && !mod->get_blackbox_attribute(worker.ignore_wb)) {
log("Deleting now unused module %s.\n", log_id(mod));
design->remove(mod);
to_remove.insert(mod);
}
for (auto mod : to_remove)
design->remove(mod);
}
log_pop();