mirror of https://github.com/YosysHQ/yosys.git
xilinx: use specify blocks in place of abc9_{arrival,required}
This commit is contained in:
Eddie Hung
parent
0e7c55e2a7
commit
577545488a
15
README.md
15
README.md
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@ -364,25 +364,14 @@ Verilog Attributes and non-standard features
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it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
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from inserting another pad cell on it.
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- The module attribute ``abc9_box_id`` specifies a positive integer linking a
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blackbox or whitebox definition to a corresponding entry in a `abc9`
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box-file.
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- The module attribute ``abc9_box`` is a boolean specifying a blackbox or
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whitebox definition for use by `abc9`.
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- The port attribute ``abc9_carry`` marks the carry-in (if an input port) and
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carry-out (if output port) ports of a box. This information is necessary for
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`abc9` to preserve the integrity of carry-chains. Specifying this attribute
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onto a bus port will affect only its most significant bit.
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- The output port attribute ``abc9_arrival`` specifies an integer, or a string
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of space-separated integers to be used as the arrival time of this blackbox
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port. It can be used, for example, to specify the clk-to-Q delay of a flip-
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flop output for consideration during `abc9` techmapping.
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- The input port attribute ``abc9_required`` specifies an integer, or a string
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of space-separated integers to be used as the required time of this blackbox
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port. It can be used, for example, to specify the setup-time of a flip-flop
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input for consideration during `abc9` techmapping.
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- The module attribute ``abc9_flop`` is a boolean marking the module as a
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flip-flop. This allows `abc9` to analyse its contents in order to perform
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sequential synthesis.
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@ -70,54 +70,6 @@ void check(RTLIL::Design *design)
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carry_out = port_name;
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}
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}
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auto it = w->attributes.find("\\abc9_arrival");
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if (it != w->attributes.end()) {
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int count = 0;
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if (it->second.flags == 0) {
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if (it->second.as_int() < 0)
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log_error("%s.%s has negative arrival value %d!\n", log_id(m), log_id(port_name),
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it->second.as_int());
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count++;
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}
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else
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for (const auto &tok : split_tokens(it->second.decode_string())) {
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if (tok.find_first_not_of("0123456789") != std::string::npos)
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log_error("%s.%s has non-integer arrival value '%s'!\n", log_id(m), log_id(port_name),
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tok.c_str());
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if (atoi(tok.c_str()) < 0)
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log_error("%s.%s has negative arrival value %s!\n", log_id(m), log_id(port_name),
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tok.c_str());
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count++;
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}
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if (count > 1 && count != GetSize(w))
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log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(m), log_id(port_name),
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GetSize(w), log_signal(it->second), count);
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}
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it = w->attributes.find("\\abc9_required");
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if (it != w->attributes.end()) {
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int count = 0;
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if (it->second.flags == 0) {
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if (it->second.as_int() < 0)
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log_error("%s.%s has negative required value %d!\n", log_id(m), log_id(port_name),
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it->second.as_int());
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count++;
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}
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else
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for (const auto &tok : split_tokens(it->second.decode_string())) {
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if (tok.find_first_not_of("0123456789") != std::string::npos)
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log_error("%s.%s has non-integer required value '%s'!\n", log_id(m), log_id(port_name),
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tok.c_str());
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if (atoi(tok.c_str()) < 0)
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log_error("%s.%s has negative required value %s!\n", log_id(m), log_id(port_name),
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tok.c_str());
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count++;
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}
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if (count > 1 && count != GetSize(w))
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log_error("%s.%s is %d bits wide but abc9_required = %s has %d value(s)!\n", log_id(m), log_id(port_name),
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GetSize(w), log_signal(it->second), count);
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}
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}
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if (carry_in != IdString() && carry_out == IdString())
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@ -428,16 +380,15 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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void prep_delays(RTLIL::Design *design)
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{
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pool<Module*> flops;
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// Derive and collect all blackbox modules, and collect all blackbox instantiations
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pool<Module*> derived;
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std::vector<Cell*> cells;
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dict<IdString,dict<IdString,std::vector<int>>> requireds_cache;
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for (auto module : design->selected_modules()) {
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if (module->processes.size() > 0) {
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log("Skipping module %s as it contains processes.\n", log_id(module));
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continue;
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}
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cells.clear();
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for (auto cell : module->cells()) {
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if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_), ID($__ABC9_DELAY)))
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continue;
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@ -447,119 +398,186 @@ void prep_delays(RTLIL::Design *design)
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continue;
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if (!inst_module->get_blackbox_attribute())
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continue;
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if (inst_module->get_bool_attribute(ID(abc9_flop))) {
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IdString derived_type = inst_module->derive(design, cell->parameters);
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inst_module = design->module(derived_type);
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log_assert(inst_module);
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flops.insert(inst_module);
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continue; // because all flop required times
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// will be captured in the flop box
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}
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if (inst_module->attributes.count(ID(abc9_box)))
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continue;
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IdString derived_type = inst_module->derive(design, cell->parameters);
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inst_module = design->module(derived_type);
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log_assert(inst_module);
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derived.insert(inst_module);
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cells.emplace_back(cell);
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}
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}
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for (auto cell : cells) {
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RTLIL::Module* inst_module = module->design->module(cell->type);
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log_assert(inst_module);
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auto &cell_requireds = requireds_cache[cell->type];
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for (auto &conn : cell->connections_) {
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auto port_wire = inst_module->wire(conn.first);
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if (!port_wire->port_input)
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// Transform all $specify3 and $specrule to abc9_{arrival,required} attributes
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std::vector<Module*> flops;
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dict<SigBit, int> arrivals, requireds;
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pool<Wire*> ports;
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std::stringstream ss;
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for (auto module : derived) {
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if (module->get_bool_attribute(ID(abc9_flop)))
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flops.push_back(module);
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arrivals.clear();
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requireds.clear();
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for (auto cell : module->cells()) {
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if (cell->type == ID($specify3)) {
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auto src = cell->getPort(ID(SRC));
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auto dat = cell->getPort(ID(DAT));
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auto dst = cell->getPort(ID(DST));
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for (const auto &c : src.chunks())
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if (!c.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
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for (const auto &c : dat.chunks())
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if (!c.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where DAT '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dat));
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for (const auto &c : dst.chunks())
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if (!c.wire->port_output)
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log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
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if (!cell->getParam(ID(EDGE_EN)).as_bool())
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continue;
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int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
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int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
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int max = std::max(rise_max,fall_max);
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if (max < 0) {
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log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
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continue;
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}
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for (auto d : dst)
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arrivals[d] = std::max(arrivals[d], max);
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}
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else if (cell->type == ID($specrule)) {
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auto type = cell->getParam(ID(TYPE)).decode_string();
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if (type != "$setup" && type != "$setuphold")
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continue;
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auto src = cell->getPort(ID(SRC));
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auto dst = cell->getPort(ID(DST));
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for (const auto &c : src.chunks())
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if (!c.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
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for (const auto &c : dst.chunks())
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if (!c.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
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int setup = cell->getParam(ID(T_LIMIT)).as_int();
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if (setup < 0) {
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log_warning("Module '%s' contains specify cell '%s' with T_LIMIT < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
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continue;
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}
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for (const auto &s : src)
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requireds[s] = std::max(requireds[s], setup);
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}
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}
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auto r = cell_requireds.insert(conn.first);
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auto &requireds = r.first->second;
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if (r.second) {
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auto it = port_wire->attributes.find("\\abc9_required");
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if (it == port_wire->attributes.end())
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continue;
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if (it->second.flags == 0) {
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int delay = it->second.as_int();
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requireds.emplace_back(delay);
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}
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if (arrivals.empty() && requireds.empty())
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continue;
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ports.clear();
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for (const auto &i : arrivals)
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ports.insert(i.first.wire);
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for (auto wire : ports) {
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log_assert(wire->port_output);
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ss.str("");
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if (GetSize(wire) == 1)
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wire->attributes[ID(abc9_arrival)] = arrivals.at(SigBit(wire,0));
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else {
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bool first = true;
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for (auto b : SigSpec(wire)) {
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if (first)
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first = false;
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else
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for (const auto &tok : split_tokens(it->second.decode_string())) {
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int delay = atoi(tok.c_str());
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requireds.push_back(delay);
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}
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ss << " ";
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auto it = arrivals.find(b);
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if (it == arrivals.end())
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ss << "0";
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else
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ss << it->second;
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}
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wire->attributes[ID(abc9_arrival)] = ss.str();
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}
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}
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if (requireds.empty())
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continue;
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SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
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auto it = requireds.begin();
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for (int i = 0; i < GetSize(conn.second); ++i) {
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#ifndef NDEBUG
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if (ys_debug(1)) {
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static std::set<std::pair<IdString,IdString>> seen;
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if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]);
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}
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#endif
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auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
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box->setPort(ID(I), conn.second[i]);
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box->setPort(ID(O), O[i]);
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box->setParam(ID(DELAY), *it);
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if (requireds.size() > 1)
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it++;
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conn.second[i] = O[i];
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ports.clear();
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for (const auto &i : requireds)
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ports.insert(i.first.wire);
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for (auto wire : ports) {
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log_assert(wire->port_input);
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ss.str("");
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if (GetSize(wire) == 1)
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wire->attributes[ID(abc9_required)] = requireds.at(SigBit(wire,0));
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else {
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bool first = true;
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for (auto b : SigSpec(wire)) {
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if (first)
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first = false;
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else
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ss << " ";
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auto it = requireds.find(b);
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if (it == requireds.end())
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ss << "0";
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else
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ss << it->second;
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}
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wire->attributes[ID(abc9_required)] = ss.str();
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}
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}
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}
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int abc9_box_id = design->scratchpad_get_int("abc9_ops.box_id");
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std::stringstream ss;
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for (auto flop_module : flops) {
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int num_inputs = 0, num_outputs = 0;
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for (auto port_name : flop_module->ports) {
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auto wire = flop_module->wire(port_name);
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log_assert(GetSize(wire) == 1);
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if (wire->port_input) num_inputs++;
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if (wire->port_output) num_outputs++;
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}
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log_assert(num_outputs == 1);
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// Insert $__ABC9_DELAY cells on all cells that instantiate blackboxes
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// with (* abc9_required *) attributes
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dict<IdString,dict<IdString,std::vector<int>>> requireds_cache;
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for (auto cell : cells) {
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auto module = cell->module;
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RTLIL::Module* inst_module = module->design->module(cell->type);
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log_assert(inst_module);
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IdString derived_type = inst_module->derive(design, cell->parameters);
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inst_module = design->module(derived_type);
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log_assert(inst_module);
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auto r = flop_module->attributes.insert(ID(abc9_box_id));
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if (r.second)
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r.first->second = ++abc9_box_id;
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ss << log_id(flop_module) << " " << r.first->second.as_int();
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ss << " " << (flop_module->get_bool_attribute(ID::whitebox) ? "1" : "0");
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ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
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ss << "#";
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bool first = true;
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for (auto port_name : flop_module->ports) {
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auto wire = flop_module->wire(port_name);
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if (!wire->port_input)
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auto &cell_requireds = requireds_cache[cell->type];
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for (auto &conn : cell->connections_) {
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auto port_wire = inst_module->wire(conn.first);
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if (!port_wire->port_input)
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continue;
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if (first)
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first = false;
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else
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ss << " ";
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ss << log_id(wire);
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}
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ss << " abc9_ff.Q" << std::endl;
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first = true;
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for (auto port_name : flop_module->ports) {
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auto wire = flop_module->wire(port_name);
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if (!wire->port_input)
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auto r = cell_requireds.insert(conn.first);
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auto &requireds = r.first->second;
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if (r.second) {
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auto it = port_wire->attributes.find("\\abc9_required");
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if (it == port_wire->attributes.end())
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continue;
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if (it->second.flags == 0) {
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int delay = it->second.as_int();
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requireds.emplace_back(delay);
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}
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else
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for (const auto &tok : split_tokens(it->second.decode_string())) {
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int delay = atoi(tok.c_str());
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requireds.push_back(delay);
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}
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}
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if (requireds.empty())
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continue;
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if (first)
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first = false;
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else
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ss << " ";
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ss << wire->attributes.at("\\abc9_required", 0).as_int();
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SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
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auto it = requireds.begin();
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for (int i = 0; i < GetSize(conn.second); ++i) {
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#ifndef NDEBUG
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if (ys_debug(1)) {
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static std::set<std::pair<IdString,IdString>> seen;
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if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]);
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}
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#endif
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auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
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box->setPort(ID(I), conn.second[i]);
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box->setPort(ID(O), O[i]);
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box->setParam(ID(DELAY), *it);
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if (requireds.size() > 1)
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it++;
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conn.second[i] = O[i];
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}
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}
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// Last input is 'abc9_ff.Q'
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ss << " 0" << std::endl << std::endl;
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}
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design->scratchpad_set_string("abc9_ops.box_library.flops", ss.str());
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design->scratchpad_set_int("abc9_ops.box_id", abc9_box_id);
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}
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void prep_lut(RTLIL::Design *design, int maxlut)
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@ -587,7 +605,10 @@ void prep_lut(RTLIL::Design *design, int maxlut)
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log_assert(o == d);
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int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
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int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
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specify.push_back(std::max(rise_max,fall_max));
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int max = std::max(rise_max,fall_max);
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if (max < 0)
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log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
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specify.push_back(max);
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}
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if (maxlut && GetSize(specify) > maxlut)
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continue;
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@ -618,10 +639,57 @@ void write_lut(RTLIL::Module *module, const std::string &dst) {
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void prep_box(RTLIL::Design *design)
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{
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std::stringstream ss;
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ss << design->scratchpad_get_string("abc9_ops.box_library.flops", ss.str());
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int abc9_box_id = design->scratchpad_get_int("abc9_ops.box_id");
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int abc9_box_id = 1;
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dict<IdString,std::vector<IdString>> box_ports;
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||||
for (auto module : design->modules()) {
|
||||
if (module->get_bool_attribute(ID(abc9_flop))) {
|
||||
int num_inputs = 0, num_outputs = 0;
|
||||
for (auto port_name : module->ports) {
|
||||
auto wire = module->wire(port_name);
|
||||
log_assert(GetSize(wire) == 1);
|
||||
if (wire->port_input) num_inputs++;
|
||||
if (wire->port_output) num_outputs++;
|
||||
}
|
||||
log_assert(num_outputs == 1);
|
||||
|
||||
auto r = module->attributes.insert(ID(abc9_box_id));
|
||||
if (r.second)
|
||||
r.first->second = abc9_box_id++;
|
||||
|
||||
ss << log_id(module) << " " << r.first->second.as_int();
|
||||
ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
|
||||
ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
|
||||
|
||||
ss << "#";
|
||||
bool first = true;
|
||||
for (auto port_name : module->ports) {
|
||||
auto wire = module->wire(port_name);
|
||||
if (!wire->port_input)
|
||||
continue;
|
||||
if (first)
|
||||
first = false;
|
||||
else
|
||||
ss << " ";
|
||||
ss << log_id(wire);
|
||||
}
|
||||
ss << " abc9_ff.Q" << std::endl;
|
||||
|
||||
first = true;
|
||||
for (auto port_name : module->ports) {
|
||||
auto wire = module->wire(port_name);
|
||||
if (!wire->port_input)
|
||||
continue;
|
||||
if (first)
|
||||
first = false;
|
||||
else
|
||||
ss << " ";
|
||||
ss << wire->attributes.at("\\abc9_required", 0).as_int();
|
||||
}
|
||||
// Last input is 'abc9_ff.Q'
|
||||
ss << " 0" << std::endl << std::endl;
|
||||
continue;
|
||||
}
|
||||
|
||||
auto it = module->attributes.find(ID(abc9_box));
|
||||
if (it == module->attributes.end())
|
||||
continue;
|
||||
|
|
@ -631,7 +699,33 @@ void prep_box(RTLIL::Design *design)
|
|||
dict<std::pair<SigBit,SigBit>, std::string> table;
|
||||
std::vector<SigBit> inputs;
|
||||
std::vector<SigBit> outputs;
|
||||
for (auto port_name : module->ports) {
|
||||
|
||||
auto r = box_ports.insert(module->name);
|
||||
if (r.second) {
|
||||
// Make carry in the last PI, and carry out the last PO
|
||||
// since ABC requires it this way
|
||||
IdString carry_in, carry_out;
|
||||
for (const auto &port_name : module->ports) {
|
||||
auto w = module->wire(port_name);
|
||||
log_assert(w);
|
||||
if (w->get_bool_attribute("\\abc9_carry")) {
|
||||
log_assert(w->port_input != w->port_output);
|
||||
if (w->port_input)
|
||||
carry_in = port_name;
|
||||
else if (w->port_output)
|
||||
carry_out = port_name;
|
||||
}
|
||||
else
|
||||
r.first->second.push_back(port_name);
|
||||
}
|
||||
|
||||
if (carry_in != IdString()) {
|
||||
r.first->second.push_back(carry_in);
|
||||
r.first->second.push_back(carry_out);
|
||||
}
|
||||
}
|
||||
|
||||
for (auto port_name : r.first->second) {
|
||||
auto wire = module->wire(port_name);
|
||||
if (wire->port_input)
|
||||
for (int i = 0; i < GetSize(wire); i++)
|
||||
|
|
@ -654,17 +748,29 @@ void prep_box(RTLIL::Design *design)
|
|||
int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
|
||||
int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
|
||||
int max = std::max(rise_max,fall_max);
|
||||
for (auto s : src)
|
||||
for (auto d : dst) {
|
||||
auto r = table.insert(std::make_pair(s,d));
|
||||
if (max < 0)
|
||||
log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
|
||||
if (cell->getParam(ID(FULL)).as_bool()) {
|
||||
for (auto s : src)
|
||||
for (auto d : dst) {
|
||||
auto r = table.insert(std::make_pair(s,d));
|
||||
log_assert(r.second);
|
||||
r.first->second = std::to_string(max);
|
||||
}
|
||||
}
|
||||
else {
|
||||
log_assert(GetSize(src) == GetSize(dst));
|
||||
for (auto i = 0; i < GetSize(src); i++) {
|
||||
auto r = table.insert(std::make_pair(src[i],dst[i]));
|
||||
log_assert(r.second);
|
||||
r.first->second = std::to_string(max);
|
||||
}
|
||||
}
|
||||
}
|
||||
auto r = module->attributes.insert(ID(abc9_box_id));
|
||||
log_assert(r.second);
|
||||
r.first->second = ++abc9_box_id;
|
||||
auto r2 = module->attributes.insert(ID(abc9_box_id));
|
||||
log_assert(r2.second);
|
||||
ss << log_id(module) << " " << abc9_box_id;
|
||||
r2.first->second = abc9_box_id++;
|
||||
ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
|
||||
ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
|
||||
bool first = true;
|
||||
|
|
@ -700,17 +806,17 @@ void prep_box(RTLIL::Design *design)
|
|||
ss << std::endl;
|
||||
}
|
||||
|
||||
// ABC expects at least one box
|
||||
if (ss.tellp() == 0)
|
||||
ss << "(dummy) 1 0 0 0";
|
||||
|
||||
design->scratchpad_set_string("abc9_ops.box_library", ss.str());
|
||||
design->scratchpad_set_int("abc9_ops.box_id", abc9_box_id);
|
||||
}
|
||||
|
||||
void write_box(RTLIL::Module *module, const std::string &dst) {
|
||||
std::ofstream ofs(dst);
|
||||
log_assert(ofs.is_open());
|
||||
ofs << module->design->scratchpad_get_string("abc9_ops.box_library");
|
||||
// ABC expects at least one box
|
||||
if (ofs.tellp() == 0)
|
||||
ofs << "(dummy) 1 0 0 0";
|
||||
ofs.close();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -477,18 +477,14 @@ endmodule
|
|||
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDRE (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D,
|
||||
(* invertible_pin = "IS_R_INVERTED" *)
|
||||
(* abc9_required=404 *)
|
||||
input R
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
|
|
@ -496,44 +492,58 @@ module FDRE (
|
|||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_R_INVERTED = 1'b0;
|
||||
initial Q <= INIT;
|
||||
generate case (|IS_C_INVERTED)
|
||||
generate
|
||||
case (|IS_C_INVERTED)
|
||||
1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
endcase endgenerate
|
||||
endcase
|
||||
if (!IS_C_INVERTED)
|
||||
specify
|
||||
if (CE) (posedge C => (Q : D)) = 303;
|
||||
//$setup(D , posedge C, -46); // Negative times not currently supported
|
||||
$setup(CE, posedge C, 109);
|
||||
$setup(R , posedge C, 404);
|
||||
endspecify
|
||||
else
|
||||
specify
|
||||
if (CE) (negedge C => (Q : D)) = 303;
|
||||
//if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
|
||||
$setup(CE, negedge C, 109);
|
||||
$setup(R , negedge C, 404);
|
||||
endspecify
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDRE_1 (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D,
|
||||
(* abc9_required=404 *)
|
||||
input R
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
|
||||
specify
|
||||
if (CE) (negedge C => (Q : D)) = 303;
|
||||
//if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
|
||||
$setup(CE, negedge C, 109);
|
||||
$setup(R , negedge C, 404);
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDSE (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D,
|
||||
(* invertible_pin = "IS_S_INVERTED" *)
|
||||
(* abc9_required=404 *)
|
||||
input S
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
|
|
@ -541,28 +551,46 @@ module FDSE (
|
|||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_S_INVERTED = 1'b0;
|
||||
initial Q <= INIT;
|
||||
generate case (|IS_C_INVERTED)
|
||||
generate
|
||||
case (|IS_C_INVERTED)
|
||||
1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
endcase endgenerate
|
||||
endcase
|
||||
if (!IS_C_INVERTED)
|
||||
specify
|
||||
if (CE) (posedge C => (Q : D)) = 303;
|
||||
//if (CE) $setup(D , posedge C, -46); // Negative times not currently supported
|
||||
$setup(CE, posedge C, 109);
|
||||
$setup(S , posedge C, 404);
|
||||
endspecify
|
||||
else
|
||||
specify
|
||||
if (CE) (negedge C => (Q : D)) = 303;
|
||||
//if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
|
||||
$setup(CE, negedge C, 109);
|
||||
$setup(S , negedge C, 404);
|
||||
endspecify
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDSE_1 (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D,
|
||||
(* abc9_required=404 *)
|
||||
input S
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
|
||||
specify
|
||||
if (CE) (negedge C => (Q : D)) = 303;
|
||||
//if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
|
||||
$setup(CE, negedge C, 109);
|
||||
$setup(S , negedge C, 404);
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
module FDRSE (
|
||||
|
|
@ -571,7 +599,6 @@ module FDRSE (
|
|||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
(* invertible_pin = "IS_CE_INVERTED" *)
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
input D,
|
||||
|
|
@ -603,18 +630,14 @@ endmodule
|
|||
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDCE (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
(* invertible_pin = "IS_CLR_INVERTED" *)
|
||||
(* abc9_required=764 *)
|
||||
input CLR,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
|
|
@ -622,46 +645,60 @@ module FDCE (
|
|||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_CLR_INVERTED = 1'b0;
|
||||
initial Q <= INIT;
|
||||
generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
|
||||
generate
|
||||
case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
|
||||
2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
endcase endgenerate
|
||||
endcase
|
||||
if (!IS_C_INVERTED)
|
||||
specify
|
||||
if (CE) (posedge C => (Q : D)) = 303;
|
||||
//if (CE) $setup(D , posedge C, -46); // Negative times not currently supported
|
||||
$setup(CE , posedge C, 109);
|
||||
$setup(CLR, posedge C, 764);
|
||||
endspecify
|
||||
else
|
||||
specify
|
||||
if (CE) (negedge C => (Q : D)) = 303;
|
||||
//if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
|
||||
$setup(CE , negedge C, 109);
|
||||
$setup(CLR, negedge C, 764);
|
||||
endspecify
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDCE_1 (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
(* abc9_required=764 *)
|
||||
input CLR,
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
|
||||
specify
|
||||
if (CE) (negedge C => (Q : D)) = 303;
|
||||
//if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
|
||||
$setup(CE , negedge C, 109);
|
||||
$setup(CLR, negedge C, 764);
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDPE (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D,
|
||||
(* invertible_pin = "IS_PRE_INVERTED" *)
|
||||
(* abc9_required=764 *)
|
||||
input PRE
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
|
|
@ -674,25 +711,42 @@ module FDPE (
|
|||
2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
endcase endgenerate
|
||||
endcase
|
||||
if (!IS_C_INVERTED)
|
||||
specify
|
||||
if (CE) (posedge C => (Q : D)) = 303;
|
||||
//if (CE) $setup(D , posedge C, -46); // Negative times not currently supported
|
||||
$setup(CE , posedge C, 109);
|
||||
$setup(PRE, posedge C, 764);
|
||||
endspecify
|
||||
else
|
||||
specify
|
||||
if (CE) (negedge C => (Q : D)) = 303;
|
||||
//if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
|
||||
$setup(CE , negedge C, 109);
|
||||
$setup(PRE, negedge C, 764);
|
||||
endspecify
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDPE_1 (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D,
|
||||
(* abc9_required=764 *)
|
||||
input PRE
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
|
||||
specify
|
||||
if (CE) (negedge C => (Q : D)) = 303;
|
||||
//if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
|
||||
$setup(CE , negedge C, 109);
|
||||
$setup(PRE, negedge C, 764);
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
module FDCPE (
|
||||
|
|
@ -1303,33 +1357,13 @@ module RAM16X1D_1 (
|
|||
endmodule
|
||||
|
||||
module RAM32X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
(* abc9_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
(* abc9_required=453 *)
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
(* abc9_required=654 *)
|
||||
input WE,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
|
||||
(* abc9_required=245 *)
|
||||
input A0,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/clBLM_R.sdf#L798
|
||||
(* abc9_required=208 *)
|
||||
input A1,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
|
||||
(* abc9_required=147 *)
|
||||
input A2,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
|
||||
(* abc9_required=68 *)
|
||||
input A3,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
|
||||
(* abc9_required=66 *)
|
||||
input A4,
|
||||
input A0, A1, A2, A3, A4,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
|
||||
);
|
||||
parameter INIT = 32'h0;
|
||||
|
|
@ -1341,35 +1375,61 @@ module RAM32X1D (
|
|||
assign DPO = mem[dpra];
|
||||
wire clk = WCLK ^ IS_WCLK_INVERTED;
|
||||
always @(posedge clk) if (WE) mem[a] <= D;
|
||||
generate
|
||||
if (!IS_WCLK_INVERTED)
|
||||
specify
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
if (WE) (posedge WCLK => (SPO : D)) = 1153;
|
||||
if (WE) (posedge WCLK => (DPO : D)) = 1153;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
$setup(D , posedge WCLK, 453);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
$setup(WE, posedge WCLK, 654);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
|
||||
$setup(A0, posedge WCLK, 245);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
|
||||
$setup(A1, posedge WCLK, 208);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
|
||||
$setup(A2, posedge WCLK, 147);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
|
||||
$setup(A3, posedge WCLK, 68);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
|
||||
$setup(A4, posedge WCLK, 66);
|
||||
endspecify
|
||||
else
|
||||
specify
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
if (WE) (negedge WCLK => (SPO : D)) = 1153;
|
||||
if (WE) (negedge WCLK => (DPO : D)) = 1153;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
$setup(D , negedge WCLK, 453);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
$setup(WE, negedge WCLK, 654);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
|
||||
$setup(A0, negedge WCLK, 245);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
|
||||
$setup(A1, negedge WCLK, 208);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
|
||||
$setup(A2, negedge WCLK, 147);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
|
||||
$setup(A3, negedge WCLK, 68);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
|
||||
$setup(A4, negedge WCLK, 66);
|
||||
endspecify
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module RAM32X1D_1 (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
(* abc9_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
(* abc9_required=453 *)
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
(* abc9_required=654 *)
|
||||
input WE,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
|
||||
(* abc9_required=245 *)
|
||||
input A0,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/clBLM_R.sdf#L798
|
||||
(* abc9_required=208 *)
|
||||
input A1,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
|
||||
(* abc9_required=147 *)
|
||||
input A2,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
|
||||
(* abc9_required=68 *)
|
||||
input A3,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
|
||||
(* abc9_required=66 *)
|
||||
input A4,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
|
||||
);
|
||||
|
|
@ -1382,39 +1442,35 @@ module RAM32X1D_1 (
|
|||
assign DPO = mem[dpra];
|
||||
wire clk = WCLK ^ IS_WCLK_INVERTED;
|
||||
always @(negedge clk) if (WE) mem[a] <= D;
|
||||
specify
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
if (WE) (negedge WCLK => (SPO : D)) = 1153;
|
||||
if (WE) (negedge WCLK => (DPO : D)) = 1153;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
$setup(D , negedge WCLK, 453);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
$setup(WE, negedge WCLK, 654);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
|
||||
$setup(A0, negedge WCLK, 245);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
|
||||
$setup(A1, negedge WCLK, 208);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
|
||||
$setup(A2, negedge WCLK, 147);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
|
||||
$setup(A3, negedge WCLK, 68);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
|
||||
$setup(A4, negedge WCLK, 66);
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
module RAM64X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
(* abc9_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
(* abc9_required=453 *)
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
(* abc9_required=654 *)
|
||||
input WE,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
|
||||
(* abc9_required=362 *)
|
||||
input A0,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
|
||||
(* abc9_required=245 *)
|
||||
input A1,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
|
||||
(* abc9_required=208 *)
|
||||
input A2,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
|
||||
(* abc9_required=147 *)
|
||||
input A3,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
|
||||
(* abc9_required=68 *)
|
||||
input A4,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
|
||||
(* abc9_required=66 *)
|
||||
input A5,
|
||||
input A0, A1, A2, A3, A4, A5,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
|
||||
);
|
||||
parameter INIT = 64'h0;
|
||||
|
|
@ -1426,39 +1482,62 @@ module RAM64X1D (
|
|||
assign DPO = mem[dpra];
|
||||
wire clk = WCLK ^ IS_WCLK_INVERTED;
|
||||
always @(posedge clk) if (WE) mem[a] <= D;
|
||||
generate
|
||||
if (!IS_WCLK_INVERTED)
|
||||
specify
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
if (WE) (posedge WCLK => (SPO : D)) = 1153;
|
||||
if (WE) (posedge WCLK => (DPO : D)) = 1153;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
$setup(D , posedge WCLK, 453);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
$setup(WE, posedge WCLK, 654);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
|
||||
$setup(A0, posedge WCLK, 362);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
|
||||
$setup(A1, posedge WCLK, 245);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
|
||||
$setup(A2, posedge WCLK, 208);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
|
||||
$setup(A3, posedge WCLK, 147);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
|
||||
$setup(A4, posedge WCLK, 68);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
|
||||
$setup(A5, posedge WCLK, 66);
|
||||
endspecify
|
||||
else
|
||||
specify
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
if (WE) (negedge WCLK => (SPO : D)) = 1153;
|
||||
if (WE) (negedge WCLK => (DPO : D)) = 1153;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
$setup(D , negedge WCLK, 453);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
$setup(WE, negedge WCLK, 654);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
|
||||
$setup(A0, negedge WCLK, 362);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
|
||||
$setup(A1, negedge WCLK, 245);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
|
||||
$setup(A2, negedge WCLK, 208);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
|
||||
$setup(A3, negedge WCLK, 147);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
|
||||
$setup(A4, negedge WCLK, 68);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
|
||||
$setup(A5, negedge WCLK, 66);
|
||||
endspecify
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module RAM64X1D_1 (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
(* abc9_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
(* abc9_required=453 *)
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
(* abc9_required=654 *)
|
||||
input WE,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
|
||||
(* abc9_required=362 *)
|
||||
input A0,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
|
||||
(* abc9_required=245 *)
|
||||
input A1,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
|
||||
(* abc9_required=208 *)
|
||||
input A2,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
|
||||
(* abc9_required=147 *)
|
||||
input A3,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
|
||||
(* abc9_required=68 *)
|
||||
input A4,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
|
||||
(* abc9_required=66 *)
|
||||
input A5,
|
||||
input A0, A1, A2, A3, A4, A5,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
|
||||
);
|
||||
parameter INIT = 64'h0;
|
||||
|
|
@ -1470,21 +1549,35 @@ module RAM64X1D_1 (
|
|||
assign DPO = mem[dpra];
|
||||
wire clk = WCLK ^ IS_WCLK_INVERTED;
|
||||
always @(negedge clk) if (WE) mem[a] <= D;
|
||||
specify
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
if (WE) (negedge WCLK => (SPO : D)) = 1153;
|
||||
if (WE) (negedge WCLK => (DPO : D)) = 1153;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
$setup(D , negedge WCLK, 453);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
$setup(WE, negedge WCLK, 654);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
|
||||
$setup(A0, negedge WCLK, 362);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
|
||||
$setup(A1, negedge WCLK, 245);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
|
||||
$setup(A2, negedge WCLK, 208);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
|
||||
$setup(A3, negedge WCLK, 147);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
|
||||
$setup(A4, negedge WCLK, 68);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
|
||||
$setup(A5, negedge WCLK, 66);
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
module RAM128X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
// plus 208ps to cross MUXF7
|
||||
(* abc9_arrival=1359 *)
|
||||
output DPO, SPO,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
(* abc9_required=453 *)
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
(* abc9_required=654 *)
|
||||
input WE,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
|
||||
(* abc9_required="616 362 245 208 147 68 66" *)
|
||||
|
|
@ -1498,6 +1591,46 @@ module RAM128X1D (
|
|||
assign DPO = mem[DPRA];
|
||||
wire clk = WCLK ^ IS_WCLK_INVERTED;
|
||||
always @(posedge clk) if (WE) mem[A] <= D;
|
||||
generate
|
||||
if (!IS_WCLK_INVERTED)
|
||||
specify
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
// plus 208ps to cross MUXF7
|
||||
if (WE) (posedge WCLK => (SPO : D)) = 1359;
|
||||
if (WE) (posedge WCLK => (DPO : D)) = 1359;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
$setup(D , posedge WCLK, 453);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
$setup(WE, posedge WCLK, 654);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
|
||||
$setup(A[0], posedge WCLK, 616);
|
||||
$setup(A[1], posedge WCLK, 362);
|
||||
$setup(A[2], posedge WCLK, 245);
|
||||
$setup(A[3], posedge WCLK, 208);
|
||||
$setup(A[4], posedge WCLK, 147);
|
||||
$setup(A[5], posedge WCLK, 68);
|
||||
$setup(A[6], posedge WCLK, 66);
|
||||
endspecify
|
||||
else
|
||||
specify
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
// plus 208ps to cross MUXF7
|
||||
if (WE) (negedge WCLK => (SPO : D)) = 1359;
|
||||
if (WE) (negedge WCLK => (DPO : D)) = 1359;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
$setup(D , negedge WCLK, 453);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
$setup(WE, negedge WCLK, 654);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
|
||||
$setup(A[0], negedge WCLK, 616);
|
||||
$setup(A[1], negedge WCLK, 362);
|
||||
$setup(A[2], negedge WCLK, 245);
|
||||
$setup(A[3], negedge WCLK, 208);
|
||||
$setup(A[4], negedge WCLK, 147);
|
||||
$setup(A[5], negedge WCLK, 68);
|
||||
$setup(A[6], negedge WCLK, 66);
|
||||
endspecify
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module RAM256X1D (
|
||||
|
|
@ -1521,43 +1654,19 @@ endmodule
|
|||
// Multi port.
|
||||
|
||||
module RAM32M (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
|
||||
(* abc9_arrival="1153 1188" *)
|
||||
output [1:0] DOA,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
|
||||
(* abc9_arrival="1161 1187" *)
|
||||
output [1:0] DOB,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
|
||||
(* abc9_arrival="1158 1180" *)
|
||||
output [1:0] DOC,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
|
||||
(* abc9_arrival="1163 1190" *)
|
||||
output [1:0] DOD,
|
||||
input [4:0] ADDRA, ADDRB, ADDRC,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792-L802
|
||||
(* abc9_required="245 208 147 68 66" *)
|
||||
input [4:0] ADDRD,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
|
||||
(* abc9_required="453 384" *)
|
||||
input [1:0] DIA,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
|
||||
(* abc9_required="461 354" *)
|
||||
input [1:0] DIB,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
|
||||
(* abc9_required="457 375" *)
|
||||
input [1:0] DIC,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
|
||||
(* abc9_required="310 334" *)
|
||||
input [1:0] DID,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
(* abc9_required=654 *)
|
||||
input WE
|
||||
);
|
||||
parameter [63:0] INIT_A = 64'h0000000000000000;
|
||||
|
|
@ -1581,6 +1690,87 @@ module RAM32M (
|
|||
mem_c[2*ADDRD+:2] <= DIC;
|
||||
mem_d[2*ADDRD+:2] <= DID;
|
||||
end
|
||||
generate
|
||||
if (!IS_WCLK_INVERTED)
|
||||
specify
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
|
||||
if (WE) (posedge WCLK => (DOA[0] : DIA[0])) = 1153;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
|
||||
if (WE) (posedge WCLK => (DOA[1] : DIA[1])) = 1188;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
if (WE) (posedge WCLK => (DOB[0] : DIB[0])) = 1161;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
|
||||
if (WE) (posedge WCLK => (DOB[1] : DIB[1])) = 1187;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
|
||||
if (WE) (posedge WCLK => (DOC[0] : DIC[0])) = 1158;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
|
||||
if (WE) (posedge WCLK => (DOC[1] : DIC[1])) = 1180;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
|
||||
if (WE) (posedge WCLK => (DOD[0] : DID[0])) = 1163;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
|
||||
if (WE) (posedge WCLK => (DOD[1] : DID[1])) = 1190;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
$setup(ADDRD[0], posedge WCLK, 245);
|
||||
$setup(ADDRD[1], posedge WCLK, 208);
|
||||
$setup(ADDRD[2], posedge WCLK, 147);
|
||||
$setup(ADDRD[3], posedge WCLK, 68);
|
||||
$setup(ADDRD[4], posedge WCLK, 66);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
|
||||
$setup(DIA[0], posedge WCLK, 453);
|
||||
$setup(DIA[1], posedge WCLK, 384);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
|
||||
$setup(DIB[0], posedge WCLK, 461);
|
||||
$setup(DIB[1], posedge WCLK, 354);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
|
||||
$setup(DIC[0], posedge WCLK, 457);
|
||||
$setup(DIC[1], posedge WCLK, 375);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
|
||||
$setup(DID[0], posedge WCLK, 310);
|
||||
$setup(DID[1], posedge WCLK, 334);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
$setup(WE, posedge WCLK, 654);
|
||||
endspecify
|
||||
else
|
||||
specify
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
|
||||
if (WE) (negedge WCLK => (DOA[0] : DIA[0])) = 1153;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
|
||||
if (WE) (negedge WCLK => (DOA[1] : DIA[1])) = 1188;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
if (WE) (negedge WCLK => (DOB[0] : DIB[0])) = 1161;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
|
||||
if (WE) (negedge WCLK => (DOB[1] : DIB[1])) = 1187;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
|
||||
if (WE) (negedge WCLK => (DOC[0] : DIC[0])) = 1158;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
|
||||
if (WE) (negedge WCLK => (DOC[1] : DIC[1])) = 1180;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
|
||||
if (WE) (negedge WCLK => (DOD[0] : DID[0])) = 1163;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
|
||||
if (WE) (negedge WCLK => (DOD[1] : DID[1])) = 1190;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
$setup(ADDRD[0], negedge WCLK, 245);
|
||||
$setup(ADDRD[1], negedge WCLK, 208);
|
||||
$setup(ADDRD[2], negedge WCLK, 147);
|
||||
$setup(ADDRD[3], negedge WCLK, 68);
|
||||
$setup(ADDRD[4], negedge WCLK, 66);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
|
||||
$setup(DIA[0], negedge WCLK, 453);
|
||||
$setup(DIA[1], negedge WCLK, 384);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
|
||||
$setup(DIB[0], negedge WCLK, 461);
|
||||
$setup(DIB[1], negedge WCLK, 354);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
|
||||
$setup(DIC[0], negedge WCLK, 457);
|
||||
$setup(DIC[1], negedge WCLK, 375);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
|
||||
$setup(DID[0], negedge WCLK, 310);
|
||||
$setup(DID[1], negedge WCLK, 334);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
$setup(WE, posedge WCLK, 654);
|
||||
endspecify
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
module RAM32M16 (
|
||||
|
|
@ -1653,39 +1843,19 @@ module RAM32M16 (
|
|||
endmodule
|
||||
|
||||
module RAM64M (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
|
||||
(* abc9_arrival=1153 *)
|
||||
output DOA,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
(* abc9_arrival=1161 *)
|
||||
output DOB,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
|
||||
(* abc9_arrival=1158 *)
|
||||
output DOC,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
|
||||
(* abc9_arrival=1163 *)
|
||||
output DOD,
|
||||
input [5:0] ADDRA, ADDRB, ADDRC,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
|
||||
(* abc9_required="362 245 208 147 68 66" *)
|
||||
input [5:0] ADDRD,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
|
||||
(* abc9_required=384 *)
|
||||
input DIA,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
|
||||
(* abc9_required=354 *)
|
||||
input DIB,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
|
||||
(* abc9_required=375 *)
|
||||
input DIC,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
|
||||
(* abc9_required=310 *)
|
||||
input DID,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
(* abc9_required=654 *)
|
||||
input WE
|
||||
);
|
||||
parameter [63:0] INIT_A = 64'h0000000000000000;
|
||||
|
|
@ -1709,6 +1879,64 @@ module RAM64M (
|
|||
mem_c[ADDRD] <= DIC;
|
||||
mem_d[ADDRD] <= DID;
|
||||
end
|
||||
generate
|
||||
if (!IS_WCLK_INVERTED)
|
||||
specify
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
|
||||
if (WE) (posedge WCLK => (DOA : DIA)) = 1153;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
if (WE) (posedge WCLK => (DOB : DIB)) = 1161;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
|
||||
if (WE) (posedge WCLK => (DOC : DIC)) = 1158;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
|
||||
if (WE) (posedge WCLK => (DOD : DID)) = 1163;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
|
||||
$setup(ADDRD[0], posedge WCLK, 362);
|
||||
$setup(ADDRD[1], posedge WCLK, 245);
|
||||
$setup(ADDRD[2], posedge WCLK, 208);
|
||||
$setup(ADDRD[3], posedge WCLK, 147);
|
||||
$setup(ADDRD[4], posedge WCLK, 68);
|
||||
$setup(ADDRD[5], posedge WCLK, 66);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
|
||||
$setup(DIA, posedge WCLK, 384);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
|
||||
$setup(DIB, posedge WCLK, 354);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
|
||||
$setup(DIC, posedge WCLK, 375);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
|
||||
$setup(DID, posedge WCLK, 310);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
$setup(WE, posedge WCLK, 654);
|
||||
endspecify
|
||||
else
|
||||
specify
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
|
||||
if (WE) (negedge WCLK => (DOA : DIA)) = 1153;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
if (WE) (negedge WCLK => (DOB : DIB)) = 1161;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
|
||||
if (WE) (negedge WCLK => (DOC : DIC)) = 1158;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
|
||||
if (WE) (negedge WCLK => (DOD : DID)) = 1163;
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
|
||||
$setup(ADDRD[0], negedge WCLK, 362);
|
||||
$setup(ADDRD[1], negedge WCLK, 245);
|
||||
$setup(ADDRD[2], negedge WCLK, 208);
|
||||
$setup(ADDRD[3], negedge WCLK, 147);
|
||||
$setup(ADDRD[4], negedge WCLK, 68);
|
||||
$setup(ADDRD[5], negedge WCLK, 66);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
|
||||
$setup(DIA, negedge WCLK, 384);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
|
||||
$setup(DIB, negedge WCLK, 354);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
|
||||
$setup(DIC, negedge WCLK, 375);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
|
||||
$setup(DID, negedge WCLK, 310);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
$setup(WE, negedge WCLK, 654);
|
||||
endspecify
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module RAM64M8 (
|
||||
|
|
|
|||
Loading…
Reference in New Issue