mirror of https://github.com/YosysHQ/yosys.git
blackbox: re-use existing Module::makeblackbox() method
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@ -48,31 +48,7 @@ struct BlackboxPass : public Pass {
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for (auto module : design->selected_whole_modules_warn())
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{
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pool<Cell*> remove_cells;
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pool<Wire*> remove_wires;
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for (auto cell : module->cells())
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remove_cells.insert(cell);
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for (auto wire : module->wires())
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if (wire->port_id == 0)
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remove_wires.insert(wire);
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for (auto it = module->memories.begin(); it != module->memories.end(); ++it)
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delete it->second;
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module->memories.clear();
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for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
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delete it->second;
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module->processes.clear();
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module->new_connections(std::vector<RTLIL::SigSig>());
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for (auto cell : remove_cells)
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module->remove(cell);
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module->remove(remove_wires);
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module->makeblackbox();
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module->set_bool_attribute(ID::blackbox);
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}
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}
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