mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #2105 from whitequark/split-flatten-off-techmap
Split `flatten` from `techmap` and simplify it
This commit is contained in:
clairexen
GitHub
commit
fbd0d8d5f0
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@ -1885,6 +1885,18 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
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return cell;
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}
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RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other)
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{
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RTLIL::Memory *mem = new RTLIL::Memory;
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mem->name = name;
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mem->width = other->width;
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mem->start_offset = other->start_offset;
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mem->size = other->size;
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mem->attributes = other->attributes;
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memories[mem->name] = mem;
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return mem;
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}
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#define DEF_METHOD(_func, _y_size, _type) \
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RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
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RTLIL::Cell *cell = addCell(name, _type); \
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@ -1170,6 +1170,8 @@ public:
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RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
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RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
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RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);
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// The add* methods create a cell and return the created cell. All signals must exist in advance.
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RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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@ -1,4 +1,5 @@
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OBJS += passes/techmap/flatten.o
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OBJS += passes/techmap/techmap.o
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OBJS += passes/techmap/simplemap.o
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OBJS += passes/techmap/dfflibmap.o
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@ -0,0 +1,357 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/utils.h"
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#include "kernel/sigtools.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void apply_prefix(IdString prefix, IdString &id)
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{
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if (id[0] == '\\')
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id = stringf("%s.%s", prefix.c_str(), id.c_str()+1);
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else
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id = stringf("$flatten%s.%s", prefix.c_str(), id.c_str());
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}
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void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
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{
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vector<SigChunk> chunks = sig;
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for (auto &chunk : chunks)
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if (chunk.wire != nullptr) {
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IdString wire_name = chunk.wire->name;
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apply_prefix(prefix, wire_name);
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log_assert(module->wire(wire_name) != nullptr);
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chunk.wire = module->wire(wire_name);
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}
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sig = chunks;
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}
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struct FlattenWorker
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{
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bool ignore_wb = false;
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void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, std::vector<RTLIL::Cell*> &new_cells)
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{
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if (tpl->processes.size() != 0) {
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log("Flattening yielded processes:");
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for (auto &it : tpl->processes)
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log(" %s",log_id(it.first));
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log("\n");
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log_error("Flattening yielded processes -> this is not supported.\n");
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}
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pool<string> extra_src_attrs = cell->get_strpool_attribute(ID::src);
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dict<IdString, IdString> memory_renames;
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for (auto &it : tpl->memories) {
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IdString m_name = it.first;
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apply_prefix(cell->name, m_name);
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RTLIL::Memory *m = module->addMemory(m_name, it.second);
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if (m->attributes.count(ID::src))
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m->add_strpool_attribute(ID::src, extra_src_attrs);
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memory_renames[it.first] = m->name;
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design->select(module, m);
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}
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dict<IdString, IdString> positional_ports;
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dict<Wire*, IdString> temp_renamed_wires;
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for (auto tpl_w : tpl->wires())
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{
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if (tpl_w->port_id > 0)
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{
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IdString posportname = stringf("$%d", tpl_w->port_id);
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positional_ports.emplace(posportname, tpl_w->name);
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}
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IdString w_name = tpl_w->name;
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apply_prefix(cell->name, w_name);
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RTLIL::Wire *w = module->wire(w_name);
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if (w != nullptr) {
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if (!w->get_bool_attribute(ID::hierconn)) {
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temp_renamed_wires[w] = w->name;
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module->rename(w, NEW_ID);
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w = nullptr;
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} else {
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w->attributes.erase(ID::hierconn);
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if (GetSize(w) < GetSize(tpl_w)) {
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log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
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log_id(tpl), log_id(tpl_w), log_id(module), log_id(cell));
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w->width = GetSize(tpl_w);
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}
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}
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}
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if (w == nullptr) {
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w = module->addWire(w_name, tpl_w);
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w->port_input = false;
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w->port_output = false;
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w->port_id = 0;
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if (w->attributes.count(ID::src))
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w->add_strpool_attribute(ID::src, extra_src_attrs);
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}
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design->select(module, w);
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}
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SigMap sigmap(module);
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SigMap tpl_sigmap(tpl);
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pool<SigBit> tpl_written_bits;
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for (auto tpl_cell : tpl->cells())
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for (auto &conn : tpl_cell->connections())
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if (tpl_cell->output(conn.first))
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for (auto bit : tpl_sigmap(conn.second))
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tpl_written_bits.insert(bit);
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for (auto &conn : tpl->connections())
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for (auto bit : tpl_sigmap(conn.first))
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tpl_written_bits.insert(bit);
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SigMap port_signal_map;
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for (auto &it : cell->connections())
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{
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IdString portname = it.first;
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if (positional_ports.count(portname) > 0)
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portname = positional_ports.at(portname);
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if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) {
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if (portname.begins_with("$"))
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log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
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continue;
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}
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if (GetSize(it.second) == 0)
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continue;
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RTLIL::Wire *w = tpl->wire(portname);
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RTLIL::SigSig c;
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if (w->port_output && !w->port_input) {
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c.first = it.second;
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c.second = RTLIL::SigSpec(w);
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apply_prefix(cell->name, c.second, module);
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} else if (!w->port_output && w->port_input) {
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c.first = RTLIL::SigSpec(w);
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c.second = it.second;
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apply_prefix(cell->name, c.first, module);
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} else {
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SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second;
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apply_prefix(cell->name, sig_tpl_pf, module);
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for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) {
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if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) {
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c.first.append(sig_mod[i]);
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c.second.append(sig_tpl_pf[i]);
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} else {
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c.first.append(sig_tpl_pf[i]);
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c.second.append(sig_mod[i]);
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}
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}
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}
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if (c.second.size() > c.first.size())
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c.second.remove(c.first.size(), c.second.size() - c.first.size());
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if (c.second.size() < c.first.size())
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c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
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log_assert(c.first.size() == c.second.size());
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// connect internal and external wires
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if (sigmap(c.first).has_const())
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log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
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log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
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module->connect(c);
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}
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for (auto tpl_cell : tpl->cells())
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{
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IdString c_name = tpl_cell->name;
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apply_prefix(cell->name, c_name);
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RTLIL::Cell *c = module->addCell(c_name, tpl_cell);
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new_cells.push_back(c);
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design->select(module, c);
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for (auto &conn : c->connections())
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{
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RTLIL::SigSpec new_conn = conn.second;
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apply_prefix(cell->name, new_conn, module);
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port_signal_map.apply(new_conn);
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c->setPort(conn.first, std::move(new_conn));
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}
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if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
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IdString memid = c->getParam(ID::MEMID).decode_string();
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log_assert(memory_renames.count(memid) != 0);
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c->setParam(ID::MEMID, Const(memory_renames[memid].str()));
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}
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if (c->type == ID($mem)) {
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IdString memid = c->getParam(ID::MEMID).decode_string();
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apply_prefix(cell->name, memid);
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c->setParam(ID::MEMID, Const(memid.c_str()));
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}
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if (c->attributes.count(ID::src))
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c->add_strpool_attribute(ID::src, extra_src_attrs);
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}
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for (auto &it : tpl->connections()) {
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RTLIL::SigSig c = it;
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apply_prefix(cell->name.str(), c.first, module);
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apply_prefix(cell->name.str(), c.second, module);
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port_signal_map.apply(c.first);
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port_signal_map.apply(c.second);
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module->connect(c);
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}
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module->remove(cell);
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for (auto &it : temp_renamed_wires)
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{
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Wire *w = it.first;
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IdString name = it.second;
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IdString altname = module->uniquify(name);
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Wire *other_w = module->wire(name);
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module->rename(other_w, altname);
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module->rename(w, name);
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}
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}
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void flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool<RTLIL::Module*> &used_modules)
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{
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if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb))
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return;
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std::vector<RTLIL::Cell*> worklist = module->selected_cells();
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while (!worklist.empty())
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{
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RTLIL::Cell *cell = worklist.back();
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worklist.pop_back();
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if (!design->has(cell->type))
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continue;
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RTLIL::Module *tpl = design->module(cell->type);
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if (tpl->get_blackbox_attribute(ignore_wb))
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continue;
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if (cell->get_bool_attribute(ID::keep_hierarchy) || tpl->get_bool_attribute(ID::keep_hierarchy)) {
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log("Keeping %s.%s (found keep_hierarchy attribute).\n", log_id(module), log_id(cell));
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used_modules.insert(tpl);
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continue;
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}
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log_debug("Flattening %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
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// If a design is fully selected and has a top module defined, topological sorting ensures that all cells
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// added during flattening are black boxes, and flattening is finished in one pass. However, when flattening
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// individual modules, this isn't the case, and the newly added cells might have to be flattened further.
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flatten_cell(design, module, cell, tpl, worklist);
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}
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}
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};
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struct FlattenPass : public Pass {
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FlattenPass() : Pass("flatten", "flatten design") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" flatten [options] [selection]\n");
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log("\n");
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log("This pass flattens the design by replacing cells by their implementation. This\n");
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log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
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log("pass is using the current design as mapping library.\n");
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log("\n");
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log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
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log("flattened by this command.\n");
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log("\n");
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log(" -wb\n");
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log(" Ignore the 'whitebox' attribute on cell implementations.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing FLATTEN pass (flatten design).\n");
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log_push();
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FlattenWorker worker;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-wb") {
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worker.ignore_wb = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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RTLIL::Module *top = nullptr;
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if (design->full_selection())
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for (auto module : design->modules())
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if (module->get_bool_attribute(ID::top))
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top = module;
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pool<RTLIL::Module*> used_modules;
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if (top == nullptr)
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used_modules = design->modules();
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else
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used_modules.insert(top);
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TopoSort<RTLIL::Module*, IdString::compare_ptr_by_name<RTLIL::Module>> topo_modules;
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pool<RTLIL::Module*> worklist = used_modules;
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while (!worklist.empty()) {
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RTLIL::Module *module = worklist.pop();
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for (auto cell : module->selected_cells()) {
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RTLIL::Module *tpl = design->module(cell->type);
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if (tpl != nullptr) {
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if (topo_modules.database.count(tpl) == 0)
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worklist.insert(tpl);
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topo_modules.edge(tpl, module);
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}
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}
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}
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if (!topo_modules.sort())
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log_error("Cannot flatten a design containing recursive instantiations.\n");
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for (auto module : topo_modules.sorted)
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worker.flatten_module(design, module, used_modules);
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if (top != nullptr)
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for (auto module : design->modules().to_vector())
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if (!used_modules[module] && !module->get_blackbox_attribute(worker.ignore_wb)) {
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log("Deleting now unused module %s.\n", log_id(module));
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design->remove(module);
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}
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|
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log_pop();
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}
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} FlattenPass;
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PRIVATE_NAMESPACE_END
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|
@ -67,10 +67,6 @@ struct TechmapWorker
|
|||
pool<RTLIL::Module*> module_queue;
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||||
dict<Module*, SigMap> sigmaps;
|
||||
|
||||
pool<IdString> flatten_do_list;
|
||||
pool<IdString> flatten_done_list;
|
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pool<Cell*> flatten_keep_list;
|
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|
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pool<string> log_msg_cache;
|
||||
|
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struct TechmapWireData {
|
||||
|
|
@ -82,7 +78,6 @@ struct TechmapWorker
|
|||
|
||||
bool extern_mode = false;
|
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bool assert_mode = false;
|
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bool flatten_mode = false;
|
||||
bool recursive_mode = false;
|
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bool autoproc_mode = false;
|
||||
bool ignore_wb = false;
|
||||
|
|
@ -168,28 +163,20 @@ struct TechmapWorker
|
|||
pool<string> extra_src_attrs = cell->get_strpool_attribute(ID::src);
|
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|
||||
orig_cell_name = cell->name.str();
|
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if (!flatten_mode) {
|
||||
for (auto tpl_cell : tpl->cells())
|
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if (tpl_cell->name == ID::_TECHMAP_REPLACE_) {
|
||||
module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
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||||
break;
|
||||
}
|
||||
}
|
||||
for (auto tpl_cell : tpl->cells())
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||||
if (tpl_cell->name == ID::_TECHMAP_REPLACE_) {
|
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module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
|
||||
break;
|
||||
}
|
||||
|
||||
dict<IdString, IdString> memory_renames;
|
||||
|
||||
for (auto &it : tpl->memories) {
|
||||
IdString m_name = it.first;
|
||||
apply_prefix(cell->name, m_name);
|
||||
RTLIL::Memory *m = new RTLIL::Memory;
|
||||
m->name = m_name;
|
||||
m->width = it.second->width;
|
||||
m->start_offset = it.second->start_offset;
|
||||
m->size = it.second->size;
|
||||
m->attributes = it.second->attributes;
|
||||
RTLIL::Memory *m = module->addMemory(m_name, it.second);
|
||||
if (m->attributes.count(ID::src))
|
||||
m->add_strpool_attribute(ID::src, extra_src_attrs);
|
||||
module->memories[m->name] = m;
|
||||
memory_renames[it.first] = m->name;
|
||||
design->select(module, m);
|
||||
}
|
||||
|
|
@ -205,7 +192,7 @@ struct TechmapWorker
|
|||
IdString posportname = stringf("$%d", tpl_w->port_id);
|
||||
positional_ports.emplace(posportname, tpl_w->name);
|
||||
|
||||
if (!flatten_mode && tpl_w->get_bool_attribute(ID::techmap_autopurge) &&
|
||||
if (tpl_w->get_bool_attribute(ID::techmap_autopurge) &&
|
||||
(!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) &&
|
||||
(!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
|
||||
{
|
||||
|
|
@ -221,26 +208,16 @@ struct TechmapWorker
|
|||
apply_prefix(cell->name, w_name);
|
||||
RTLIL::Wire *w = module->wire(w_name);
|
||||
if (w != nullptr) {
|
||||
if (!flatten_mode || !w->get_bool_attribute(ID::hierconn)) {
|
||||
temp_renamed_wires[w] = w->name;
|
||||
module->rename(w, NEW_ID);
|
||||
w = nullptr;
|
||||
} else {
|
||||
w->attributes.erase(ID::hierconn);
|
||||
if (GetSize(w) < GetSize(tpl_w)) {
|
||||
log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
|
||||
log_id(tpl), log_id(tpl_w), log_id(module), log_id(cell));
|
||||
w->width = GetSize(tpl_w);
|
||||
}
|
||||
}
|
||||
temp_renamed_wires[w] = w->name;
|
||||
module->rename(w, NEW_ID);
|
||||
w = nullptr;
|
||||
}
|
||||
if (w == nullptr) {
|
||||
w = module->addWire(w_name, tpl_w);
|
||||
w->port_input = false;
|
||||
w->port_output = false;
|
||||
w->port_id = 0;
|
||||
if (!flatten_mode)
|
||||
w->attributes.erase(ID::techmap_autopurge);
|
||||
w->attributes.erase(ID::techmap_autopurge);
|
||||
if (tpl_w->get_bool_attribute(ID::_techmap_special_))
|
||||
w->attributes.clear();
|
||||
if (w->attributes.count(ID::src))
|
||||
|
|
@ -322,56 +299,37 @@ struct TechmapWorker
|
|||
|
||||
log_assert(c.first.size() == c.second.size());
|
||||
|
||||
if (flatten_mode)
|
||||
{
|
||||
// more conservative approach:
|
||||
// connect internal and external wires
|
||||
|
||||
if (sigmaps.count(module) == 0)
|
||||
sigmaps[module].set(module);
|
||||
|
||||
if (sigmaps.at(module)(c.first).has_const())
|
||||
log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
|
||||
log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
|
||||
// replace internal wires that are connected to external wires
|
||||
|
||||
if (w->port_output && !w->port_input) {
|
||||
port_signal_map.add(c.second, c.first);
|
||||
} else
|
||||
if (!w->port_output && w->port_input) {
|
||||
port_signal_map.add(c.first, c.second);
|
||||
} else {
|
||||
module->connect(c);
|
||||
extra_connect = SigSig();
|
||||
}
|
||||
else
|
||||
{
|
||||
// approach that yields nicer outputs:
|
||||
// replace internal wires that are connected to external wires
|
||||
|
||||
if (w->port_output && !w->port_input) {
|
||||
port_signal_map.add(c.second, c.first);
|
||||
} else
|
||||
if (!w->port_output && w->port_input) {
|
||||
port_signal_map.add(c.first, c.second);
|
||||
} else {
|
||||
module->connect(c);
|
||||
extra_connect = SigSig();
|
||||
}
|
||||
|
||||
for (auto &attr : w->attributes) {
|
||||
if (attr.first == ID::src)
|
||||
continue;
|
||||
auto lhs = GetSize(extra_connect.first);
|
||||
auto rhs = GetSize(extra_connect.second);
|
||||
if (lhs > rhs)
|
||||
extra_connect.first.remove(rhs, lhs-rhs);
|
||||
else if (rhs > lhs)
|
||||
extra_connect.second.remove(lhs, rhs-lhs);
|
||||
module->connect(extra_connect);
|
||||
break;
|
||||
}
|
||||
for (auto &attr : w->attributes) {
|
||||
if (attr.first == ID::src)
|
||||
continue;
|
||||
auto lhs = GetSize(extra_connect.first);
|
||||
auto rhs = GetSize(extra_connect.second);
|
||||
if (lhs > rhs)
|
||||
extra_connect.first.remove(rhs, lhs-rhs);
|
||||
else if (rhs > lhs)
|
||||
extra_connect.second.remove(lhs, rhs-lhs);
|
||||
module->connect(extra_connect);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (auto tpl_cell : tpl->cells())
|
||||
{
|
||||
IdString c_name = tpl_cell->name;
|
||||
bool techmap_replace_cell = (!flatten_mode) && (c_name == ID::_TECHMAP_REPLACE_);
|
||||
|
||||
if (techmap_replace_cell)
|
||||
if (c_name == ID::_TECHMAP_REPLACE_)
|
||||
c_name = orig_cell_name;
|
||||
else if (tpl_cell->name.begins_with("\\_TECHMAP_REPLACE_."))
|
||||
c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
|
||||
|
|
@ -381,7 +339,7 @@ struct TechmapWorker
|
|||
RTLIL::Cell *c = module->addCell(c_name, tpl_cell);
|
||||
design->select(module, c);
|
||||
|
||||
if (!flatten_mode && c->type.begins_with("\\$"))
|
||||
if (c->type.begins_with("\\$"))
|
||||
c->type = c->type.substr(1);
|
||||
|
||||
vector<IdString> autopurge_ports;
|
||||
|
|
@ -426,7 +384,7 @@ struct TechmapWorker
|
|||
if (c->attributes.count(ID::src))
|
||||
c->add_strpool_attribute(ID::src, extra_src_attrs);
|
||||
|
||||
if (techmap_replace_cell)
|
||||
if (c_name == ID::_TECHMAP_REPLACE_)
|
||||
for (auto attr : cell->attributes)
|
||||
if (!c->attributes.count(attr.first))
|
||||
c->attributes[attr.first] = attr.second;
|
||||
|
|
@ -499,22 +457,6 @@ struct TechmapWorker
|
|||
continue;
|
||||
}
|
||||
|
||||
if (flatten_mode) {
|
||||
bool keepit = cell->get_bool_attribute(ID::keep_hierarchy);
|
||||
for (auto &tpl_name : celltypeMap.at(cell_type))
|
||||
if (map->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy))
|
||||
keepit = true;
|
||||
if (keepit) {
|
||||
if (!flatten_keep_list[cell]) {
|
||||
log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell));
|
||||
flatten_keep_list.insert(cell);
|
||||
}
|
||||
if (!flatten_done_list[cell->type])
|
||||
flatten_do_list.insert(cell->type);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
for (auto &conn : cell->connections())
|
||||
{
|
||||
RTLIL::SigSpec sig = sigmap(conn.second);
|
||||
|
|
@ -564,172 +506,171 @@ struct TechmapWorker
|
|||
if (tpl->get_blackbox_attribute(ignore_wb))
|
||||
continue;
|
||||
|
||||
if (!flatten_mode)
|
||||
std::string extmapper_name;
|
||||
|
||||
if (tpl->get_bool_attribute(ID::techmap_simplemap))
|
||||
extmapper_name = "simplemap";
|
||||
|
||||
if (tpl->get_bool_attribute(ID::techmap_maccmap))
|
||||
extmapper_name = "maccmap";
|
||||
|
||||
if (tpl->attributes.count(ID::techmap_wrap))
|
||||
extmapper_name = "wrap";
|
||||
|
||||
if (!extmapper_name.empty())
|
||||
{
|
||||
std::string extmapper_name;
|
||||
cell->type = cell_type;
|
||||
|
||||
if (tpl->get_bool_attribute(ID::techmap_simplemap))
|
||||
extmapper_name = "simplemap";
|
||||
|
||||
if (tpl->get_bool_attribute(ID::techmap_maccmap))
|
||||
extmapper_name = "maccmap";
|
||||
|
||||
if (tpl->attributes.count(ID::techmap_wrap))
|
||||
extmapper_name = "wrap";
|
||||
|
||||
if (!extmapper_name.empty())
|
||||
if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
|
||||
{
|
||||
cell->type = cell_type;
|
||||
std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
|
||||
|
||||
if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
|
||||
for (auto &c : cell->parameters)
|
||||
m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
|
||||
|
||||
if (extmapper_name == "wrap")
|
||||
m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
|
||||
|
||||
RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
|
||||
RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
|
||||
|
||||
if (extmapper_module == nullptr)
|
||||
{
|
||||
std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
|
||||
extmapper_module = extmapper_design->addModule(m_name);
|
||||
RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
|
||||
|
||||
for (auto &c : cell->parameters)
|
||||
m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
|
||||
extmapper_cell->set_src_attribute(cell->get_src_attribute());
|
||||
|
||||
if (extmapper_name == "wrap")
|
||||
m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
|
||||
|
||||
RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
|
||||
RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
|
||||
|
||||
if (extmapper_module == nullptr)
|
||||
{
|
||||
extmapper_module = extmapper_design->addModule(m_name);
|
||||
RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
|
||||
|
||||
extmapper_cell->set_src_attribute(cell->get_src_attribute());
|
||||
|
||||
int port_counter = 1;
|
||||
for (auto &c : extmapper_cell->connections_) {
|
||||
RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
|
||||
if (w->name.in(ID::Y, ID::Q))
|
||||
w->port_output = true;
|
||||
else
|
||||
w->port_input = true;
|
||||
w->port_id = port_counter++;
|
||||
c.second = w;
|
||||
}
|
||||
|
||||
extmapper_module->fixup_ports();
|
||||
extmapper_module->check();
|
||||
|
||||
if (extmapper_name == "simplemap") {
|
||||
log("Creating %s with simplemap.\n", log_id(extmapper_module));
|
||||
if (simplemap_mappers.count(extmapper_cell->type) == 0)
|
||||
log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
|
||||
simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
|
||||
extmapper_module->remove(extmapper_cell);
|
||||
}
|
||||
|
||||
if (extmapper_name == "maccmap") {
|
||||
log("Creating %s with maccmap.\n", log_id(extmapper_module));
|
||||
if (extmapper_cell->type != ID($macc))
|
||||
log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
|
||||
maccmap(extmapper_module, extmapper_cell);
|
||||
extmapper_module->remove(extmapper_cell);
|
||||
}
|
||||
|
||||
if (extmapper_name == "wrap") {
|
||||
std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
|
||||
log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
|
||||
mkdebug.on();
|
||||
Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
|
||||
log_continue = true;
|
||||
}
|
||||
int port_counter = 1;
|
||||
for (auto &c : extmapper_cell->connections_) {
|
||||
RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
|
||||
if (w->name.in(ID::Y, ID::Q))
|
||||
w->port_output = true;
|
||||
else
|
||||
w->port_input = true;
|
||||
w->port_id = port_counter++;
|
||||
c.second = w;
|
||||
}
|
||||
|
||||
cell->type = extmapper_module->name;
|
||||
cell->parameters.clear();
|
||||
|
||||
if (!extern_mode || in_recursion) {
|
||||
tpl = extmapper_module;
|
||||
goto use_wrapper_tpl;
|
||||
}
|
||||
|
||||
auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
|
||||
if (!log_msg_cache.count(msg)) {
|
||||
log_msg_cache.insert(msg);
|
||||
log("%s\n", msg.c_str());
|
||||
}
|
||||
log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
|
||||
}
|
||||
else
|
||||
{
|
||||
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
|
||||
if (!log_msg_cache.count(msg)) {
|
||||
log_msg_cache.insert(msg);
|
||||
log("%s\n", msg.c_str());
|
||||
}
|
||||
log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
|
||||
extmapper_module->fixup_ports();
|
||||
extmapper_module->check();
|
||||
|
||||
if (extmapper_name == "simplemap") {
|
||||
if (simplemap_mappers.count(cell->type) == 0)
|
||||
log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type));
|
||||
simplemap_mappers.at(cell->type)(module, cell);
|
||||
log("Creating %s with simplemap.\n", log_id(extmapper_module));
|
||||
if (simplemap_mappers.count(extmapper_cell->type) == 0)
|
||||
log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
|
||||
simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
|
||||
extmapper_module->remove(extmapper_cell);
|
||||
}
|
||||
|
||||
if (extmapper_name == "maccmap") {
|
||||
if (cell->type != ID($macc))
|
||||
log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
|
||||
maccmap(module, cell);
|
||||
log("Creating %s with maccmap.\n", log_id(extmapper_module));
|
||||
if (extmapper_cell->type != ID($macc))
|
||||
log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
|
||||
maccmap(extmapper_module, extmapper_cell);
|
||||
extmapper_module->remove(extmapper_cell);
|
||||
}
|
||||
|
||||
module->remove(cell);
|
||||
cell = nullptr;
|
||||
if (extmapper_name == "wrap") {
|
||||
std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
|
||||
log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
|
||||
mkdebug.on();
|
||||
Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
|
||||
log_continue = true;
|
||||
}
|
||||
}
|
||||
|
||||
did_something = true;
|
||||
mapped_cell = true;
|
||||
break;
|
||||
cell->type = extmapper_module->name;
|
||||
cell->parameters.clear();
|
||||
|
||||
if (!extern_mode || in_recursion) {
|
||||
tpl = extmapper_module;
|
||||
goto use_wrapper_tpl;
|
||||
}
|
||||
|
||||
auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
|
||||
if (!log_msg_cache.count(msg)) {
|
||||
log_msg_cache.insert(msg);
|
||||
log("%s\n", msg.c_str());
|
||||
}
|
||||
log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
|
||||
}
|
||||
else
|
||||
{
|
||||
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
|
||||
if (!log_msg_cache.count(msg)) {
|
||||
log_msg_cache.insert(msg);
|
||||
log("%s\n", msg.c_str());
|
||||
}
|
||||
log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
|
||||
|
||||
if (extmapper_name == "simplemap") {
|
||||
if (simplemap_mappers.count(cell->type) == 0)
|
||||
log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type));
|
||||
simplemap_mappers.at(cell->type)(module, cell);
|
||||
}
|
||||
|
||||
if (extmapper_name == "maccmap") {
|
||||
if (cell->type != ID($macc))
|
||||
log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
|
||||
maccmap(module, cell);
|
||||
}
|
||||
|
||||
module->remove(cell);
|
||||
cell = nullptr;
|
||||
}
|
||||
|
||||
for (auto &conn : cell->connections()) {
|
||||
if (conn.first.begins_with("$"))
|
||||
continue;
|
||||
if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0)
|
||||
continue;
|
||||
if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
|
||||
goto next_tpl;
|
||||
parameters[conn.first] = conn.second.as_const();
|
||||
}
|
||||
did_something = true;
|
||||
mapped_cell = true;
|
||||
break;
|
||||
}
|
||||
|
||||
if (0) {
|
||||
next_tpl:
|
||||
for (auto &conn : cell->connections()) {
|
||||
if (conn.first.begins_with("$"))
|
||||
continue;
|
||||
if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0)
|
||||
continue;
|
||||
if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
|
||||
goto next_tpl;
|
||||
parameters[conn.first] = conn.second.as_const();
|
||||
}
|
||||
|
||||
if (0) {
|
||||
next_tpl:
|
||||
continue;
|
||||
}
|
||||
|
||||
if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
|
||||
parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type));
|
||||
|
||||
for (auto &conn : cell->connections()) {
|
||||
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) {
|
||||
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
|
||||
for (auto &bit : v)
|
||||
bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
|
||||
}
|
||||
|
||||
if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
|
||||
parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type));
|
||||
|
||||
for (auto &conn : cell->connections()) {
|
||||
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) {
|
||||
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
|
||||
for (auto &bit : v)
|
||||
bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
|
||||
}
|
||||
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) {
|
||||
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
|
||||
for (auto &bit : v)
|
||||
if (bit.wire != nullptr)
|
||||
bit = RTLIL::SigBit(RTLIL::State::Sx);
|
||||
parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
|
||||
}
|
||||
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) {
|
||||
auto sig = sigmap(conn.second);
|
||||
RTLIL::Const value(State::Sx, sig.size());
|
||||
for (int i = 0; i < sig.size(); i++) {
|
||||
auto it = init_bits.find(sig[i]);
|
||||
if (it != init_bits.end()) {
|
||||
value[i] = it->second;
|
||||
}
|
||||
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) {
|
||||
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
|
||||
for (auto &bit : v)
|
||||
if (bit.wire != nullptr)
|
||||
bit = RTLIL::SigBit(RTLIL::State::Sx);
|
||||
parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
|
||||
}
|
||||
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) {
|
||||
auto sig = sigmap(conn.second);
|
||||
RTLIL::Const value(State::Sx, sig.size());
|
||||
for (int i = 0; i < sig.size(); i++) {
|
||||
auto it = init_bits.find(sig[i]);
|
||||
if (it != init_bits.end()) {
|
||||
value[i] = it->second;
|
||||
}
|
||||
parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value);
|
||||
}
|
||||
parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value);
|
||||
}
|
||||
}
|
||||
|
||||
{
|
||||
int unique_bit_id_counter = 0;
|
||||
dict<RTLIL::SigBit, int> unique_bit_id;
|
||||
unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
|
||||
|
|
@ -787,13 +728,9 @@ struct TechmapWorker
|
|||
}
|
||||
}
|
||||
|
||||
if (flatten_mode) {
|
||||
techmap_do_cache[tpl] = true;
|
||||
} else {
|
||||
RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
|
||||
if (constmapped_tpl != nullptr)
|
||||
tpl = constmapped_tpl;
|
||||
}
|
||||
RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
|
||||
if (constmapped_tpl != nullptr)
|
||||
tpl = constmapped_tpl;
|
||||
|
||||
if (techmap_do_cache.count(tpl) == 0)
|
||||
{
|
||||
|
|
@ -1333,97 +1270,4 @@ struct TechmapPass : public Pass {
|
|||
}
|
||||
} TechmapPass;
|
||||
|
||||
struct FlattenPass : public Pass {
|
||||
FlattenPass() : Pass("flatten", "flatten design") { }
|
||||
void help() YS_OVERRIDE
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" flatten [options] [selection]\n");
|
||||
log("\n");
|
||||
log("This pass flattens the design by replacing cells by their implementation. This\n");
|
||||
log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
|
||||
log("pass is using the current design as mapping library.\n");
|
||||
log("\n");
|
||||
log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
|
||||
log("flattened by this command.\n");
|
||||
log("\n");
|
||||
log(" -wb\n");
|
||||
log(" Ignore the 'whitebox' attribute on cell implementations.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
log_header(design, "Executing FLATTEN pass (flatten design).\n");
|
||||
log_push();
|
||||
|
||||
TechmapWorker worker;
|
||||
worker.flatten_mode = true;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
if (args[argidx] == "-wb") {
|
||||
worker.ignore_wb = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
|
||||
dict<IdString, pool<IdString>> celltypeMap;
|
||||
for (auto module : design->modules())
|
||||
celltypeMap[module->name].insert(module->name);
|
||||
for (auto &i : celltypeMap)
|
||||
i.second.sort(RTLIL::sort_by_id_str());
|
||||
|
||||
RTLIL::Module *top_mod = nullptr;
|
||||
if (design->full_selection())
|
||||
for (auto mod : design->modules())
|
||||
if (mod->get_bool_attribute(ID::top))
|
||||
top_mod = mod;
|
||||
|
||||
pool<RTLIL::Cell*> handled_cells;
|
||||
if (top_mod != nullptr) {
|
||||
worker.flatten_do_list.insert(top_mod->name);
|
||||
while (!worker.flatten_do_list.empty()) {
|
||||
auto mod = design->module(*worker.flatten_do_list.begin());
|
||||
while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
|
||||
worker.flatten_done_list.insert(mod->name);
|
||||
worker.flatten_do_list.erase(mod->name);
|
||||
}
|
||||
} else {
|
||||
for (auto mod : design->modules().to_vector())
|
||||
while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
|
||||
}
|
||||
|
||||
log_suppressed();
|
||||
log("No more expansions possible.\n");
|
||||
|
||||
if (top_mod != nullptr)
|
||||
{
|
||||
pool<IdString> used_modules, new_used_modules;
|
||||
new_used_modules.insert(top_mod->name);
|
||||
while (!new_used_modules.empty()) {
|
||||
pool<IdString> queue;
|
||||
queue.swap(new_used_modules);
|
||||
for (auto modname : queue)
|
||||
used_modules.insert(modname);
|
||||
for (auto modname : queue)
|
||||
for (auto cell : design->module(modname)->cells())
|
||||
if (design->module(cell->type) && !used_modules[cell->type])
|
||||
new_used_modules.insert(cell->type);
|
||||
}
|
||||
|
||||
for (auto mod : design->modules().to_vector())
|
||||
if (!used_modules[mod->name] && !mod->get_blackbox_attribute(worker.ignore_wb)) {
|
||||
log("Deleting now unused module %s.\n", log_id(mod));
|
||||
design->remove(mod);
|
||||
}
|
||||
}
|
||||
|
||||
log_pop();
|
||||
}
|
||||
} FlattenPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
|
|||
Loading…
Reference in New Issue