From 6ac54a74fe9764f82b16ff3b8f06baf71f4a224b Mon Sep 17 00:00:00 2001 From: whitequark Date: Tue, 2 Jun 2020 23:15:13 +0000 Subject: [PATCH 01/13] flatten: split from techmap. Although the two passes started out very similar, they diverged over time and now have little in common. Moreover, `techmap` is extremely complex while `flatten` does not have to be, and this complexity interferes with improving `flatten`. --- passes/techmap/Makefile.inc | 1 + passes/techmap/flatten.cc | 1148 +++++++++++++++++++++++++++++++++++ passes/techmap/techmap.cc | 93 --- 3 files changed, 1149 insertions(+), 93 deletions(-) create mode 100644 passes/techmap/flatten.cc diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 873286608..a54b4913d 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -1,4 +1,5 @@ +OBJS += passes/techmap/flatten.o OBJS += passes/techmap/techmap.o OBJS += passes/techmap/simplemap.o OBJS += passes/techmap/dfflibmap.o diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc new file mode 100644 index 000000000..b0c8ea907 --- /dev/null +++ b/passes/techmap/flatten.cc @@ -0,0 +1,1148 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/utils.h" +#include "kernel/sigtools.h" +#include "libs/sha1/sha1.h" + +#include +#include +#include + +#include "simplemap.h" + +YOSYS_NAMESPACE_BEGIN + +// see maccmap.cc +extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false); + +YOSYS_NAMESPACE_END + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +void apply_prefix(IdString prefix, IdString &id) +{ + if (id[0] == '\\') + id = stringf("%s.%s", prefix.c_str(), id.c_str()+1); + else + id = stringf("$techmap%s.%s", prefix.c_str(), id.c_str()); +} + +void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) +{ + vector chunks = sig; + for (auto &chunk : chunks) + if (chunk.wire != nullptr) { + IdString wire_name = chunk.wire->name; + apply_prefix(prefix, wire_name); + log_assert(module->wire(wire_name) != nullptr); + chunk.wire = module->wire(wire_name); + } + sig = chunks; +} + +struct TechmapWorker +{ + dict simplemap_mappers; + dict>, RTLIL::Module*> techmap_cache; + dict techmap_do_cache; + pool module_queue; + dict sigmaps; + + pool flatten_do_list; + pool flatten_done_list; + pool flatten_keep_list; + + pool log_msg_cache; + + struct TechmapWireData { + RTLIL::Wire *wire; + RTLIL::SigSpec value; + }; + + typedef dict> TechmapWires; + + bool extern_mode = false; + bool assert_mode = false; + bool flatten_mode = false; + bool recursive_mode = false; + bool autoproc_mode = false; + bool ignore_wb = false; + + std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose) + { + std::string constmap_info; + dict> connbits_map; + + for (auto &conn : cell->connections()) + for (int i = 0; i < GetSize(conn.second); i++) { + RTLIL::SigBit bit = sigmap(conn.second[i]); + if (bit.wire == nullptr) { + if (verbose) + log(" Constant input on bit %d of port %s: %s\n", i, log_id(conn.first), log_signal(bit)); + constmap_info += stringf("|%s %d %d", log_id(conn.first), i, bit.data); + } else if (connbits_map.count(bit)) { + if (verbose) + log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first), + connbits_map.at(bit).second, log_id(connbits_map.at(bit).first)); + constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i, + log_id(connbits_map.at(bit).first), connbits_map.at(bit).second); + } else { + connbits_map.emplace(bit, std::make_pair(conn.first, i)); + constmap_info += stringf("|%s %d", log_id(conn.first), i); + } + } + + return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str()); + } + + TechmapWires techmap_find_special_wires(RTLIL::Module *module) + { + TechmapWires result; + + if (module == nullptr) + return result; + + for (auto w : module->wires()) { + const char *p = w->name.c_str(); + if (*p == '$') + continue; + + const char *q = strrchr(p+1, '.'); + if (q) + p = q; + + if (!strncmp(p, "\\_TECHMAP_", 10)) { + TechmapWireData record; + record.wire = w; + record.value = w; + result[p].push_back(record); + w->set_bool_attribute(ID::keep); + w->set_bool_attribute(ID::_techmap_special_); + } + } + + if (!result.empty()) { + SigMap sigmap(module); + for (auto &it1 : result) + for (auto &it2 : it1.second) + sigmap.apply(it2.value); + } + + return result; + } + + void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl) + { + if (tpl->processes.size() != 0) { + log("Technology map yielded processes:"); + for (auto &it : tpl->processes) + log(" %s",log_id(it.first)); + log("\n"); + if (autoproc_mode) { + Pass::call_on_module(tpl->design, tpl, "proc"); + log_assert(GetSize(tpl->processes) == 0); + } else + log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n"); + } + + std::string orig_cell_name; + pool extra_src_attrs = cell->get_strpool_attribute(ID::src); + + orig_cell_name = cell->name.str(); + if (!flatten_mode) { + for (auto tpl_cell : tpl->cells()) + if (tpl_cell->name == ID::_TECHMAP_REPLACE_) { + module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str()); + break; + } + } + + dict memory_renames; + + for (auto &it : tpl->memories) { + IdString m_name = it.first; + apply_prefix(cell->name, m_name); + RTLIL::Memory *m = new RTLIL::Memory; + m->name = m_name; + m->width = it.second->width; + m->start_offset = it.second->start_offset; + m->size = it.second->size; + m->attributes = it.second->attributes; + if (m->attributes.count(ID::src)) + m->add_strpool_attribute(ID::src, extra_src_attrs); + module->memories[m->name] = m; + memory_renames[it.first] = m->name; + design->select(module, m); + } + + dict positional_ports; + dict temp_renamed_wires; + pool autopurge_tpl_bits; + + for (auto tpl_w : tpl->wires()) + { + if (tpl_w->port_id > 0) + { + IdString posportname = stringf("$%d", tpl_w->port_id); + positional_ports.emplace(posportname, tpl_w->name); + + if (!flatten_mode && tpl_w->get_bool_attribute(ID::techmap_autopurge) && + (!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) && + (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname)))) + { + if (sigmaps.count(tpl) == 0) + sigmaps[tpl].set(tpl); + + for (auto bit : sigmaps.at(tpl)(tpl_w)) + if (bit.wire != nullptr) + autopurge_tpl_bits.insert(bit); + } + } + IdString w_name = tpl_w->name; + apply_prefix(cell->name, w_name); + RTLIL::Wire *w = module->wire(w_name); + if (w != nullptr) { + if (!flatten_mode || !w->get_bool_attribute(ID::hierconn)) { + temp_renamed_wires[w] = w->name; + module->rename(w, NEW_ID); + w = nullptr; + } else { + w->attributes.erase(ID::hierconn); + if (GetSize(w) < GetSize(tpl_w)) { + log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w), + log_id(tpl), log_id(tpl_w), log_id(module), log_id(cell)); + w->width = GetSize(tpl_w); + } + } + } + if (w == nullptr) { + w = module->addWire(w_name, tpl_w); + w->port_input = false; + w->port_output = false; + w->port_id = 0; + if (!flatten_mode) + w->attributes.erase(ID::techmap_autopurge); + if (tpl_w->get_bool_attribute(ID::_techmap_special_)) + w->attributes.clear(); + if (w->attributes.count(ID::src)) + w->add_strpool_attribute(ID::src, extra_src_attrs); + } + design->select(module, w); + + if (tpl_w->name.begins_with("\\_TECHMAP_REPLACE_.")) { + IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), tpl_w->name.c_str() + strlen("\\_TECHMAP_REPLACE_")); + Wire *replace_w = module->addWire(replace_name, tpl_w); + module->connect(replace_w, w); + } + } + + SigMap tpl_sigmap(tpl); + pool tpl_written_bits; + + for (auto tpl_cell : tpl->cells()) + for (auto &conn : tpl_cell->connections()) + if (tpl_cell->output(conn.first)) + for (auto bit : tpl_sigmap(conn.second)) + tpl_written_bits.insert(bit); + for (auto &conn : tpl->connections()) + for (auto bit : tpl_sigmap(conn.first)) + tpl_written_bits.insert(bit); + + SigMap port_signal_map; + + for (auto &it : cell->connections()) + { + IdString portname = it.first; + if (positional_ports.count(portname) > 0) + portname = positional_ports.at(portname); + if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) { + if (portname.begins_with("$")) + log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str()); + continue; + } + + if (GetSize(it.second) == 0) + continue; + + RTLIL::Wire *w = tpl->wire(portname); + RTLIL::SigSig c, extra_connect; + + if (w->port_output && !w->port_input) { + c.first = it.second; + c.second = RTLIL::SigSpec(w); + apply_prefix(cell->name, c.second, module); + extra_connect.first = c.second; + extra_connect.second = c.first; + } else if (!w->port_output && w->port_input) { + c.first = RTLIL::SigSpec(w); + c.second = it.second; + apply_prefix(cell->name, c.first, module); + extra_connect.first = c.first; + extra_connect.second = c.second; + } else { + SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second; + apply_prefix(cell->name, sig_tpl_pf, module); + for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) { + if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) { + c.first.append(sig_mod[i]); + c.second.append(sig_tpl_pf[i]); + } else { + c.first.append(sig_tpl_pf[i]); + c.second.append(sig_mod[i]); + } + } + extra_connect.first = sig_tpl_pf; + extra_connect.second = sig_mod; + } + + if (c.second.size() > c.first.size()) + c.second.remove(c.first.size(), c.second.size() - c.first.size()); + + if (c.second.size() < c.first.size()) + c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size())); + + log_assert(c.first.size() == c.second.size()); + + if (flatten_mode) + { + // more conservative approach: + // connect internal and external wires + + if (sigmaps.count(module) == 0) + sigmaps[module].set(module); + + if (sigmaps.at(module)(c.first).has_const()) + log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n", + log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second)); + + module->connect(c); + } + else + { + // approach that yields nicer outputs: + // replace internal wires that are connected to external wires + + if (w->port_output && !w->port_input) { + port_signal_map.add(c.second, c.first); + } else + if (!w->port_output && w->port_input) { + port_signal_map.add(c.first, c.second); + } else { + module->connect(c); + extra_connect = SigSig(); + } + + for (auto &attr : w->attributes) { + if (attr.first == ID::src) + continue; + auto lhs = GetSize(extra_connect.first); + auto rhs = GetSize(extra_connect.second); + if (lhs > rhs) + extra_connect.first.remove(rhs, lhs-rhs); + else if (rhs > lhs) + extra_connect.second.remove(lhs, rhs-lhs); + module->connect(extra_connect); + break; + } + } + } + + for (auto tpl_cell : tpl->cells()) + { + IdString c_name = tpl_cell->name; + bool techmap_replace_cell = (!flatten_mode) && (c_name == ID::_TECHMAP_REPLACE_); + + if (techmap_replace_cell) + c_name = orig_cell_name; + else if (tpl_cell->name.begins_with("\\_TECHMAP_REPLACE_.")) + c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_")); + else + apply_prefix(cell->name, c_name); + + RTLIL::Cell *c = module->addCell(c_name, tpl_cell); + design->select(module, c); + + if (!flatten_mode && c->type.begins_with("\\$")) + c->type = c->type.substr(1); + + vector autopurge_ports; + + for (auto &conn : c->connections()) + { + bool autopurge = false; + if (!autopurge_tpl_bits.empty()) { + autopurge = GetSize(conn.second) != 0; + for (auto &bit : sigmaps.at(tpl)(conn.second)) + if (!autopurge_tpl_bits.count(bit)) { + autopurge = false; + break; + } + } + + if (autopurge) { + autopurge_ports.push_back(conn.first); + } else { + RTLIL::SigSpec new_conn = conn.second; + apply_prefix(cell->name, new_conn, module); + port_signal_map.apply(new_conn); + c->setPort(conn.first, std::move(new_conn)); + } + } + + for (auto &it2 : autopurge_ports) + c->unsetPort(it2); + + if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) { + IdString memid = c->getParam(ID::MEMID).decode_string(); + log_assert(memory_renames.count(memid) != 0); + c->setParam(ID::MEMID, Const(memory_renames[memid].str())); + } + + if (c->type == ID($mem)) { + IdString memid = c->getParam(ID::MEMID).decode_string(); + apply_prefix(cell->name, memid); + c->setParam(ID::MEMID, Const(memid.c_str())); + } + + if (c->attributes.count(ID::src)) + c->add_strpool_attribute(ID::src, extra_src_attrs); + + if (techmap_replace_cell) + for (auto attr : cell->attributes) + if (!c->attributes.count(attr.first)) + c->attributes[attr.first] = attr.second; + } + + for (auto &it : tpl->connections()) { + RTLIL::SigSig c = it; + apply_prefix(cell->name.str(), c.first, module); + apply_prefix(cell->name.str(), c.second, module); + port_signal_map.apply(c.first); + port_signal_map.apply(c.second); + module->connect(c); + } + + module->remove(cell); + + for (auto &it : temp_renamed_wires) + { + Wire *w = it.first; + IdString name = it.second; + IdString altname = module->uniquify(name); + Wire *other_w = module->wire(name); + module->rename(other_w, altname); + module->rename(w, name); + } + } + + bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool &handled_cells, + const dict> &celltypeMap, bool in_recursion) + { + std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; + + if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb)) + return false; + + bool log_continue = false; + bool did_something = false; + LogMakeDebugHdl mkdebug; + + SigMap sigmap(module); + + dict init_bits; + pool remove_init_bits; + + for (auto wire : module->wires()) { + if (wire->attributes.count(ID::init)) { + Const value = wire->attributes.at(ID::init); + for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) + if (value[i] != State::Sx) + init_bits[sigmap(SigBit(wire, i))] = value[i]; + } + } + + TopoSort> cells; + dict> cell_to_inbit; + dict> outbit_to_cell; + + for (auto cell : module->selected_cells()) + { + if (handled_cells.count(cell) > 0) + continue; + + std::string cell_type = cell->type.str(); + if (in_recursion && cell->type.begins_with("\\$")) + cell_type = cell_type.substr(1); + + if (celltypeMap.count(cell_type) == 0) { + if (assert_mode && cell_type.back() != '_') + log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type)); + continue; + } + + if (flatten_mode) { + bool keepit = cell->get_bool_attribute(ID::keep_hierarchy); + for (auto &tpl_name : celltypeMap.at(cell_type)) + if (map->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy)) + keepit = true; + if (keepit) { + if (!flatten_keep_list[cell]) { + log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell)); + flatten_keep_list.insert(cell); + } + if (!flatten_done_list[cell->type]) + flatten_do_list.insert(cell->type); + continue; + } + } + + for (auto &conn : cell->connections()) + { + RTLIL::SigSpec sig = sigmap(conn.second); + sig.remove_const(); + + if (GetSize(sig) == 0) + continue; + + for (auto &tpl_name : celltypeMap.at(cell_type)) { + RTLIL::Module *tpl = map->module(tpl_name); + RTLIL::Wire *port = tpl->wire(conn.first); + if (port && port->port_input) + cell_to_inbit[cell].insert(sig.begin(), sig.end()); + if (port && port->port_output) + for (auto &bit : sig) + outbit_to_cell[bit].insert(cell); + } + } + + cells.node(cell); + } + + for (auto &it_right : cell_to_inbit) + for (auto &it_sigbit : it_right.second) + for (auto &it_left : outbit_to_cell[it_sigbit]) + cells.edge(it_left, it_right.first); + + cells.sort(); + + for (auto cell : cells.sorted) + { + log_assert(handled_cells.count(cell) == 0); + log_assert(cell == module->cell(cell->name)); + bool mapped_cell = false; + + std::string cell_type = cell->type.str(); + + if (in_recursion && cell->type.begins_with("\\$")) + cell_type = cell_type.substr(1); + + for (auto &tpl_name : celltypeMap.at(cell_type)) + { + IdString derived_name = tpl_name; + RTLIL::Module *tpl = map->module(tpl_name); + dict parameters(cell->parameters); + + if (tpl->get_blackbox_attribute(ignore_wb)) + continue; + + if (!flatten_mode) + { + std::string extmapper_name; + + if (tpl->get_bool_attribute(ID::techmap_simplemap)) + extmapper_name = "simplemap"; + + if (tpl->get_bool_attribute(ID::techmap_maccmap)) + extmapper_name = "maccmap"; + + if (tpl->attributes.count(ID::techmap_wrap)) + extmapper_name = "wrap"; + + if (!extmapper_name.empty()) + { + cell->type = cell_type; + + if ((extern_mode && !in_recursion) || extmapper_name == "wrap") + { + std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type)); + + for (auto &c : cell->parameters) + m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second)); + + if (extmapper_name == "wrap") + m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string()); + + RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design; + RTLIL::Module *extmapper_module = extmapper_design->module(m_name); + + if (extmapper_module == nullptr) + { + extmapper_module = extmapper_design->addModule(m_name); + RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell); + + extmapper_cell->set_src_attribute(cell->get_src_attribute()); + + int port_counter = 1; + for (auto &c : extmapper_cell->connections_) { + RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second)); + if (w->name.in(ID::Y, ID::Q)) + w->port_output = true; + else + w->port_input = true; + w->port_id = port_counter++; + c.second = w; + } + + extmapper_module->fixup_ports(); + extmapper_module->check(); + + if (extmapper_name == "simplemap") { + log("Creating %s with simplemap.\n", log_id(extmapper_module)); + if (simplemap_mappers.count(extmapper_cell->type) == 0) + log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type)); + simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell); + extmapper_module->remove(extmapper_cell); + } + + if (extmapper_name == "maccmap") { + log("Creating %s with maccmap.\n", log_id(extmapper_module)); + if (extmapper_cell->type != ID($macc)) + log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type)); + maccmap(extmapper_module, extmapper_cell); + extmapper_module->remove(extmapper_cell); + } + + if (extmapper_name == "wrap") { + std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string(); + log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module)); + mkdebug.on(); + Pass::call_on_module(extmapper_design, extmapper_module, cmd_string); + log_continue = true; + } + } + + cell->type = extmapper_module->name; + cell->parameters.clear(); + + if (!extern_mode || in_recursion) { + tpl = extmapper_module; + goto use_wrapper_tpl; + } + + auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type)); + if (!log_msg_cache.count(msg)) { + log_msg_cache.insert(msg); + log("%s\n", msg.c_str()); + } + log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module)); + } + else + { + auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type)); + if (!log_msg_cache.count(msg)) { + log_msg_cache.insert(msg); + log("%s\n", msg.c_str()); + } + log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str()); + + if (extmapper_name == "simplemap") { + if (simplemap_mappers.count(cell->type) == 0) + log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type)); + simplemap_mappers.at(cell->type)(module, cell); + } + + if (extmapper_name == "maccmap") { + if (cell->type != ID($macc)) + log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type)); + maccmap(module, cell); + } + + module->remove(cell); + cell = nullptr; + } + + did_something = true; + mapped_cell = true; + break; + } + + for (auto &conn : cell->connections()) { + if (conn.first.begins_with("$")) + continue; + if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0) + continue; + if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0) + goto next_tpl; + parameters[conn.first] = conn.second.as_const(); + } + + if (0) { + next_tpl: + continue; + } + + if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0) + parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type)); + + for (auto &conn : cell->connections()) { + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) { + std::vector v = sigmap(conn.second).to_sigbit_vector(); + for (auto &bit : v) + bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0); + parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); + } + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) { + std::vector v = sigmap(conn.second).to_sigbit_vector(); + for (auto &bit : v) + if (bit.wire != nullptr) + bit = RTLIL::SigBit(RTLIL::State::Sx); + parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); + } + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) { + auto sig = sigmap(conn.second); + RTLIL::Const value(State::Sx, sig.size()); + for (int i = 0; i < sig.size(); i++) { + auto it = init_bits.find(sig[i]); + if (it != init_bits.end()) { + value[i] = it->second; + } + } + parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value); + } + } + + int unique_bit_id_counter = 0; + dict unique_bit_id; + unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++; + unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++; + unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++; + unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++; + + for (auto &conn : cell->connections()) + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) { + for (auto &bit : sigmap(conn.second)) + if (unique_bit_id.count(bit) == 0) + unique_bit_id[bit] = unique_bit_id_counter++; + } + + // Find highest bit set + int bits = 0; + for (int i = 0; i < 32; i++) + if (((unique_bit_id_counter-1) & (1 << i)) != 0) + bits = i; + // Increment index by one to get number of bits + bits++; + if (tpl->avail_parameters.count(ID::_TECHMAP_BITS_CONNMAP_)) + parameters[ID::_TECHMAP_BITS_CONNMAP_] = bits; + + for (auto &conn : cell->connections()) + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) { + RTLIL::Const value; + for (auto &bit : sigmap(conn.second)) { + int val = unique_bit_id.at(bit); + for (int i = 0; i < bits; i++) { + value.bits.push_back((val & 1) != 0 ? State::S1 : State::S0); + val = val >> 1; + } + } + parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), value); + } + } + + if (0) { + use_wrapper_tpl:; + // do not register techmap_wrap modules with techmap_cache + } else { + std::pair> key(tpl_name, parameters); + auto it = techmap_cache.find(key); + if (it != techmap_cache.end()) { + tpl = it->second; + } else { + if (parameters.size() != 0) { + mkdebug.on(); + derived_name = tpl->derive(map, parameters); + tpl = map->module(derived_name); + log_continue = true; + } + techmap_cache.emplace(std::move(key), tpl); + } + } + + if (flatten_mode) { + techmap_do_cache[tpl] = true; + } else { + RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false)); + if (constmapped_tpl != nullptr) + tpl = constmapped_tpl; + } + + if (techmap_do_cache.count(tpl) == 0) + { + bool keep_running = true; + techmap_do_cache[tpl] = true; + + pool techmap_wire_names; + + while (keep_running) + { + TechmapWires twd = techmap_find_special_wires(tpl); + keep_running = false; + + for (auto &it : twd) + techmap_wire_names.insert(it.first); + + for (auto &it : twd[ID::_TECHMAP_FAIL_]) { + RTLIL::SigSpec value = it.value; + if (value.is_fully_const() && value.as_bool()) { + log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n", + derived_name.c_str(), log_id(it.wire->name), log_signal(value)); + techmap_do_cache[tpl] = false; + } + } + + if (!techmap_do_cache[tpl]) + break; + + for (auto &it : twd) + { + if (!it.first.begins_with("\\_TECHMAP_DO_") || it.second.empty()) + continue; + + auto &data = it.second.front(); + + if (!data.value.is_fully_const()) + log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(data.wire->name), log_signal(data.value)); + + techmap_wire_names.erase(it.first); + + const char *p = data.wire->name.c_str(); + const char *q = strrchr(p+1, '.'); + q = q ? q : p+1; + + std::string cmd_string = data.value.as_const().decode_string(); + + restart_eval_cmd_string: + if (cmd_string.rfind("CONSTMAP; ", 0) == 0) + { + cmd_string = cmd_string.substr(strlen("CONSTMAP; ")); + + log("Analyzing pattern of constant bits for this cell:\n"); + IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true); + log("Creating constmapped module `%s'.\n", log_id(new_tpl_name)); + log_assert(map->module(new_tpl_name) == nullptr); + + RTLIL::Module *new_tpl = map->addModule(new_tpl_name); + tpl->cloneInto(new_tpl); + + techmap_do_cache.erase(tpl); + techmap_do_cache[new_tpl] = true; + tpl = new_tpl; + + dict port_new2old_map; + dict port_connmap; + dict cellbits_to_tplbits; + + for (auto wire : tpl->wires().to_vector()) + { + if (!wire->port_input || wire->port_output) + continue; + + IdString port_name = wire->name; + tpl->rename(wire, NEW_ID); + + RTLIL::Wire *new_wire = tpl->addWire(port_name, wire); + wire->port_input = false; + wire->port_id = 0; + + for (int i = 0; i < wire->width; i++) { + port_new2old_map.emplace(RTLIL::SigBit(new_wire, i), RTLIL::SigBit(wire, i)); + port_connmap.emplace(RTLIL::SigBit(wire, i), RTLIL::SigBit(new_wire, i)); + } + } + + for (auto &conn : cell->connections()) + for (int i = 0; i < GetSize(conn.second); i++) + { + RTLIL::SigBit bit = sigmap(conn.second[i]); + RTLIL::SigBit tplbit(tpl->wire(conn.first), i); + + if (bit.wire == nullptr) + { + RTLIL::SigBit oldbit = port_new2old_map.at(tplbit); + port_connmap.at(oldbit) = bit; + } + else if (cellbits_to_tplbits.count(bit)) + { + RTLIL::SigBit oldbit = port_new2old_map.at(tplbit); + port_connmap.at(oldbit) = cellbits_to_tplbits[bit]; + } + else + cellbits_to_tplbits[bit] = tplbit; + } + + RTLIL::SigSig port_conn; + for (auto &it : port_connmap) { + port_conn.first.append(it.first); + port_conn.second.append(it.second); + } + tpl->connect(port_conn); + + tpl->check(); + goto restart_eval_cmd_string; + } + + if (cmd_string.rfind("RECURSION; ", 0) == 0) + { + cmd_string = cmd_string.substr(strlen("RECURSION; ")); + while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { } + goto restart_eval_cmd_string; + } + + Pass::call_on_module(map, tpl, cmd_string); + + log_assert(!strncmp(q, "_TECHMAP_DO_", 12)); + std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12); + while (tpl->wire(new_name) != nullptr) + new_name += "_"; + tpl->rename(data.wire->name, new_name); + + keep_running = true; + break; + } + } + + TechmapWires twd = techmap_find_special_wires(tpl); + for (auto &it : twd) { + if (it.first != ID::_TECHMAP_FAIL_ && (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && !it.first.begins_with("\\_TECHMAP_DO_") && !it.first.begins_with("\\_TECHMAP_DONE_")) + log_error("Techmap yielded unknown config wire %s.\n", log_id(it.first)); + if (techmap_do_cache[tpl]) + for (auto &it2 : it.second) + if (!it2.value.is_fully_const()) + log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(it2.wire->name), log_signal(it2.value)); + techmap_wire_names.erase(it.first); + } + + for (auto &it : techmap_wire_names) + log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", log_id(it)); + + if (recursive_mode) { + if (log_continue) { + log_header(design, "Continuing TECHMAP pass.\n"); + log_continue = false; + mkdebug.off(); + } + while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { } + } + } + + if (techmap_do_cache.at(tpl) == false) + continue; + + if (log_continue) { + log_header(design, "Continuing TECHMAP pass.\n"); + log_continue = false; + mkdebug.off(); + } + + TechmapWires twd = techmap_find_special_wires(tpl); + for (auto &it : twd) { + if (it.first.begins_with("\\_TECHMAP_REMOVEINIT_")) { + for (auto &it2 : it.second) { + auto val = it2.value.as_const(); + auto wirename = RTLIL::escape_id(it.first.substr(21, it.first.size() - 21 - 1)); + auto it = cell->connections().find(wirename); + if (it != cell->connections().end()) { + auto sig = sigmap(it->second); + for (int i = 0; i < sig.size(); i++) + if (val[i] == State::S1) + remove_init_bits.insert(sig[i]); + } + } + } + } + + if (extern_mode && !in_recursion) + { + std::string m_name = stringf("$extern:%s", log_id(tpl)); + + if (!design->module(m_name)) + { + RTLIL::Module *m = design->addModule(m_name); + tpl->cloneInto(m); + + for (auto cell : m->cells()) { + if (cell->type.begins_with("\\$")) + cell->type = cell->type.substr(1); + } + + module_queue.insert(m); + } + + log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name)); + cell->type = m_name; + cell->parameters.clear(); + } + else + { + auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type)); + if (!log_msg_cache.count(msg)) { + log_msg_cache.insert(msg); + log("%s\n", msg.c_str()); + } + log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); + techmap_module_worker(design, module, cell, tpl); + cell = nullptr; + } + did_something = true; + mapped_cell = true; + break; + } + + if (assert_mode && !mapped_cell) + log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); + + handled_cells.insert(cell); + } + + if (!remove_init_bits.empty()) { + for (auto wire : module->wires()) + if (wire->attributes.count(ID::init)) { + Const &value = wire->attributes.at(ID::init); + bool do_cleanup = true; + for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) { + SigBit bit = sigmap(SigBit(wire, i)); + if (remove_init_bits.count(bit)) + value[i] = State::Sx; + else if (value[i] != State::Sx) + do_cleanup = false; + } + if (do_cleanup) { + log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire)); + wire->attributes.erase(ID::init); + } + } + } + + if (log_continue) { + log_header(design, "Continuing TECHMAP pass.\n"); + log_continue = false; + mkdebug.off(); + } + + return did_something; + } +}; + +struct FlattenPass : public Pass { + FlattenPass() : Pass("flatten", "flatten design") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" flatten [options] [selection]\n"); + log("\n"); + log("This pass flattens the design by replacing cells by their implementation. This\n"); + log("pass is very similar to the 'techmap' pass. The only difference is that this\n"); + log("pass is using the current design as mapping library.\n"); + log("\n"); + log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n"); + log("flattened by this command.\n"); + log("\n"); + log(" -wb\n"); + log(" Ignore the 'whitebox' attribute on cell implementations.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing FLATTEN pass (flatten design).\n"); + log_push(); + + TechmapWorker worker; + worker.flatten_mode = true; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-wb") { + worker.ignore_wb = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + + dict> celltypeMap; + for (auto module : design->modules()) + celltypeMap[module->name].insert(module->name); + for (auto &i : celltypeMap) + i.second.sort(RTLIL::sort_by_id_str()); + + RTLIL::Module *top_mod = nullptr; + if (design->full_selection()) + for (auto mod : design->modules()) + if (mod->get_bool_attribute(ID::top)) + top_mod = mod; + + pool handled_cells; + if (top_mod != nullptr) { + worker.flatten_do_list.insert(top_mod->name); + while (!worker.flatten_do_list.empty()) { + auto mod = design->module(*worker.flatten_do_list.begin()); + while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { } + worker.flatten_done_list.insert(mod->name); + worker.flatten_do_list.erase(mod->name); + } + } else { + for (auto mod : design->modules().to_vector()) + while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { } + } + + log_suppressed(); + log("No more expansions possible.\n"); + + if (top_mod != nullptr) + { + pool used_modules, new_used_modules; + new_used_modules.insert(top_mod->name); + while (!new_used_modules.empty()) { + pool queue; + queue.swap(new_used_modules); + for (auto modname : queue) + used_modules.insert(modname); + for (auto modname : queue) + for (auto cell : design->module(modname)->cells()) + if (design->module(cell->type) && !used_modules[cell->type]) + new_used_modules.insert(cell->type); + } + + for (auto mod : design->modules().to_vector()) + if (!used_modules[mod->name] && !mod->get_blackbox_attribute(worker.ignore_wb)) { + log("Deleting now unused module %s.\n", log_id(mod)); + design->remove(mod); + } + } + + log_pop(); + } +} FlattenPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index c88f7bd0a..8659d0f36 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -1333,97 +1333,4 @@ struct TechmapPass : public Pass { } } TechmapPass; -struct FlattenPass : public Pass { - FlattenPass() : Pass("flatten", "flatten design") { } - void help() YS_OVERRIDE - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" flatten [options] [selection]\n"); - log("\n"); - log("This pass flattens the design by replacing cells by their implementation. This\n"); - log("pass is very similar to the 'techmap' pass. The only difference is that this\n"); - log("pass is using the current design as mapping library.\n"); - log("\n"); - log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n"); - log("flattened by this command.\n"); - log("\n"); - log(" -wb\n"); - log(" Ignore the 'whitebox' attribute on cell implementations.\n"); - log("\n"); - } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE - { - log_header(design, "Executing FLATTEN pass (flatten design).\n"); - log_push(); - - TechmapWorker worker; - worker.flatten_mode = true; - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-wb") { - worker.ignore_wb = true; - continue; - } - break; - } - extra_args(args, argidx, design); - - - dict> celltypeMap; - for (auto module : design->modules()) - celltypeMap[module->name].insert(module->name); - for (auto &i : celltypeMap) - i.second.sort(RTLIL::sort_by_id_str()); - - RTLIL::Module *top_mod = nullptr; - if (design->full_selection()) - for (auto mod : design->modules()) - if (mod->get_bool_attribute(ID::top)) - top_mod = mod; - - pool handled_cells; - if (top_mod != nullptr) { - worker.flatten_do_list.insert(top_mod->name); - while (!worker.flatten_do_list.empty()) { - auto mod = design->module(*worker.flatten_do_list.begin()); - while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { } - worker.flatten_done_list.insert(mod->name); - worker.flatten_do_list.erase(mod->name); - } - } else { - for (auto mod : design->modules().to_vector()) - while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { } - } - - log_suppressed(); - log("No more expansions possible.\n"); - - if (top_mod != nullptr) - { - pool used_modules, new_used_modules; - new_used_modules.insert(top_mod->name); - while (!new_used_modules.empty()) { - pool queue; - queue.swap(new_used_modules); - for (auto modname : queue) - used_modules.insert(modname); - for (auto modname : queue) - for (auto cell : design->module(modname)->cells()) - if (design->module(cell->type) && !used_modules[cell->type]) - new_used_modules.insert(cell->type); - } - - for (auto mod : design->modules().to_vector()) - if (!used_modules[mod->name] && !mod->get_blackbox_attribute(worker.ignore_wb)) { - log("Deleting now unused module %s.\n", log_id(mod)); - design->remove(mod); - } - } - - log_pop(); - } -} FlattenPass; - PRIVATE_NAMESPACE_END From 76c4ee4ea5cb6a3dc214f66237af22a1bedda010 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 3 Jun 2020 00:12:54 +0000 Subject: [PATCH 02/13] techmap, flatten: remove dead options. After splitting the passes, some options can never be activated, and most conditions involving them become dead. Remove them, and also all of the newly dead code. --- passes/techmap/flatten.cc | 747 +++----------------------------------- passes/techmap/techmap.cc | 403 +++++++++----------- 2 files changed, 217 insertions(+), 933 deletions(-) diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index b0c8ea907..214cda844 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -20,21 +20,11 @@ #include "kernel/yosys.h" #include "kernel/utils.h" #include "kernel/sigtools.h" -#include "libs/sha1/sha1.h" #include #include #include -#include "simplemap.h" - -YOSYS_NAMESPACE_BEGIN - -// see maccmap.cc -extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false); - -YOSYS_NAMESPACE_END - USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -61,10 +51,7 @@ void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) struct TechmapWorker { - dict simplemap_mappers; dict>, RTLIL::Module*> techmap_cache; - dict techmap_do_cache; - pool module_queue; dict sigmaps; pool flatten_do_list; @@ -73,83 +60,8 @@ struct TechmapWorker pool log_msg_cache; - struct TechmapWireData { - RTLIL::Wire *wire; - RTLIL::SigSpec value; - }; - - typedef dict> TechmapWires; - - bool extern_mode = false; - bool assert_mode = false; - bool flatten_mode = false; - bool recursive_mode = false; - bool autoproc_mode = false; bool ignore_wb = false; - std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose) - { - std::string constmap_info; - dict> connbits_map; - - for (auto &conn : cell->connections()) - for (int i = 0; i < GetSize(conn.second); i++) { - RTLIL::SigBit bit = sigmap(conn.second[i]); - if (bit.wire == nullptr) { - if (verbose) - log(" Constant input on bit %d of port %s: %s\n", i, log_id(conn.first), log_signal(bit)); - constmap_info += stringf("|%s %d %d", log_id(conn.first), i, bit.data); - } else if (connbits_map.count(bit)) { - if (verbose) - log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first), - connbits_map.at(bit).second, log_id(connbits_map.at(bit).first)); - constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i, - log_id(connbits_map.at(bit).first), connbits_map.at(bit).second); - } else { - connbits_map.emplace(bit, std::make_pair(conn.first, i)); - constmap_info += stringf("|%s %d", log_id(conn.first), i); - } - } - - return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str()); - } - - TechmapWires techmap_find_special_wires(RTLIL::Module *module) - { - TechmapWires result; - - if (module == nullptr) - return result; - - for (auto w : module->wires()) { - const char *p = w->name.c_str(); - if (*p == '$') - continue; - - const char *q = strrchr(p+1, '.'); - if (q) - p = q; - - if (!strncmp(p, "\\_TECHMAP_", 10)) { - TechmapWireData record; - record.wire = w; - record.value = w; - result[p].push_back(record); - w->set_bool_attribute(ID::keep); - w->set_bool_attribute(ID::_techmap_special_); - } - } - - if (!result.empty()) { - SigMap sigmap(module); - for (auto &it1 : result) - for (auto &it2 : it1.second) - sigmap.apply(it2.value); - } - - return result; - } - void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl) { if (tpl->processes.size() != 0) { @@ -157,25 +69,11 @@ struct TechmapWorker for (auto &it : tpl->processes) log(" %s",log_id(it.first)); log("\n"); - if (autoproc_mode) { - Pass::call_on_module(tpl->design, tpl, "proc"); - log_assert(GetSize(tpl->processes) == 0); - } else - log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n"); + log_error("Technology map yielded processes -> this is not supported.\n"); } - std::string orig_cell_name; pool extra_src_attrs = cell->get_strpool_attribute(ID::src); - orig_cell_name = cell->name.str(); - if (!flatten_mode) { - for (auto tpl_cell : tpl->cells()) - if (tpl_cell->name == ID::_TECHMAP_REPLACE_) { - module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str()); - break; - } - } - dict memory_renames; for (auto &it : tpl->memories) { @@ -196,7 +94,6 @@ struct TechmapWorker dict positional_ports; dict temp_renamed_wires; - pool autopurge_tpl_bits; for (auto tpl_w : tpl->wires()) { @@ -204,24 +101,12 @@ struct TechmapWorker { IdString posportname = stringf("$%d", tpl_w->port_id); positional_ports.emplace(posportname, tpl_w->name); - - if (!flatten_mode && tpl_w->get_bool_attribute(ID::techmap_autopurge) && - (!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) && - (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname)))) - { - if (sigmaps.count(tpl) == 0) - sigmaps[tpl].set(tpl); - - for (auto bit : sigmaps.at(tpl)(tpl_w)) - if (bit.wire != nullptr) - autopurge_tpl_bits.insert(bit); - } } IdString w_name = tpl_w->name; apply_prefix(cell->name, w_name); RTLIL::Wire *w = module->wire(w_name); if (w != nullptr) { - if (!flatten_mode || !w->get_bool_attribute(ID::hierconn)) { + if (!w->get_bool_attribute(ID::hierconn)) { temp_renamed_wires[w] = w->name; module->rename(w, NEW_ID); w = nullptr; @@ -239,20 +124,10 @@ struct TechmapWorker w->port_input = false; w->port_output = false; w->port_id = 0; - if (!flatten_mode) - w->attributes.erase(ID::techmap_autopurge); - if (tpl_w->get_bool_attribute(ID::_techmap_special_)) - w->attributes.clear(); if (w->attributes.count(ID::src)) w->add_strpool_attribute(ID::src, extra_src_attrs); } design->select(module, w); - - if (tpl_w->name.begins_with("\\_TECHMAP_REPLACE_.")) { - IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), tpl_w->name.c_str() + strlen("\\_TECHMAP_REPLACE_")); - Wire *replace_w = module->addWire(replace_name, tpl_w); - module->connect(replace_w, w); - } } SigMap tpl_sigmap(tpl); @@ -284,20 +159,16 @@ struct TechmapWorker continue; RTLIL::Wire *w = tpl->wire(portname); - RTLIL::SigSig c, extra_connect; + RTLIL::SigSig c; if (w->port_output && !w->port_input) { c.first = it.second; c.second = RTLIL::SigSpec(w); apply_prefix(cell->name, c.second, module); - extra_connect.first = c.second; - extra_connect.second = c.first; } else if (!w->port_output && w->port_input) { c.first = RTLIL::SigSpec(w); c.second = it.second; apply_prefix(cell->name, c.first, module); - extra_connect.first = c.first; - extra_connect.second = c.second; } else { SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second; apply_prefix(cell->name, sig_tpl_pf, module); @@ -310,8 +181,6 @@ struct TechmapWorker c.second.append(sig_mod[i]); } } - extra_connect.first = sig_tpl_pf; - extra_connect.second = sig_mod; } if (c.second.size() > c.first.size()) @@ -322,95 +191,34 @@ struct TechmapWorker log_assert(c.first.size() == c.second.size()); - if (flatten_mode) - { - // more conservative approach: - // connect internal and external wires + // connect internal and external wires - if (sigmaps.count(module) == 0) - sigmaps[module].set(module); + if (sigmaps.count(module) == 0) + sigmaps[module].set(module); - if (sigmaps.at(module)(c.first).has_const()) - log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n", - log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second)); + if (sigmaps.at(module)(c.first).has_const()) + log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n", + log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second)); - module->connect(c); - } - else - { - // approach that yields nicer outputs: - // replace internal wires that are connected to external wires - - if (w->port_output && !w->port_input) { - port_signal_map.add(c.second, c.first); - } else - if (!w->port_output && w->port_input) { - port_signal_map.add(c.first, c.second); - } else { - module->connect(c); - extra_connect = SigSig(); - } - - for (auto &attr : w->attributes) { - if (attr.first == ID::src) - continue; - auto lhs = GetSize(extra_connect.first); - auto rhs = GetSize(extra_connect.second); - if (lhs > rhs) - extra_connect.first.remove(rhs, lhs-rhs); - else if (rhs > lhs) - extra_connect.second.remove(lhs, rhs-lhs); - module->connect(extra_connect); - break; - } - } + module->connect(c); } for (auto tpl_cell : tpl->cells()) { IdString c_name = tpl_cell->name; - bool techmap_replace_cell = (!flatten_mode) && (c_name == ID::_TECHMAP_REPLACE_); - - if (techmap_replace_cell) - c_name = orig_cell_name; - else if (tpl_cell->name.begins_with("\\_TECHMAP_REPLACE_.")) - c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_")); - else - apply_prefix(cell->name, c_name); + apply_prefix(cell->name, c_name); RTLIL::Cell *c = module->addCell(c_name, tpl_cell); design->select(module, c); - if (!flatten_mode && c->type.begins_with("\\$")) - c->type = c->type.substr(1); - - vector autopurge_ports; - for (auto &conn : c->connections()) { - bool autopurge = false; - if (!autopurge_tpl_bits.empty()) { - autopurge = GetSize(conn.second) != 0; - for (auto &bit : sigmaps.at(tpl)(conn.second)) - if (!autopurge_tpl_bits.count(bit)) { - autopurge = false; - break; - } - } - - if (autopurge) { - autopurge_ports.push_back(conn.first); - } else { - RTLIL::SigSpec new_conn = conn.second; - apply_prefix(cell->name, new_conn, module); - port_signal_map.apply(new_conn); - c->setPort(conn.first, std::move(new_conn)); - } + RTLIL::SigSpec new_conn = conn.second; + apply_prefix(cell->name, new_conn, module); + port_signal_map.apply(new_conn); + c->setPort(conn.first, std::move(new_conn)); } - for (auto &it2 : autopurge_ports) - c->unsetPort(it2); - if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) { IdString memid = c->getParam(ID::MEMID).decode_string(); log_assert(memory_renames.count(memid) != 0); @@ -425,11 +233,6 @@ struct TechmapWorker if (c->attributes.count(ID::src)) c->add_strpool_attribute(ID::src, extra_src_attrs); - - if (techmap_replace_cell) - for (auto attr : cell->attributes) - if (!c->attributes.count(attr.first)) - c->attributes[attr.first] = attr.second; } for (auto &it : tpl->connections()) { @@ -468,18 +271,6 @@ struct TechmapWorker SigMap sigmap(module); - dict init_bits; - pool remove_init_bits; - - for (auto wire : module->wires()) { - if (wire->attributes.count(ID::init)) { - Const value = wire->attributes.at(ID::init); - for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) - if (value[i] != State::Sx) - init_bits[sigmap(SigBit(wire, i))] = value[i]; - } - } - TopoSort> cells; dict> cell_to_inbit; dict> outbit_to_cell; @@ -493,26 +284,21 @@ struct TechmapWorker if (in_recursion && cell->type.begins_with("\\$")) cell_type = cell_type.substr(1); - if (celltypeMap.count(cell_type) == 0) { - if (assert_mode && cell_type.back() != '_') - log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type)); + if (celltypeMap.count(cell_type) == 0) continue; - } - if (flatten_mode) { - bool keepit = cell->get_bool_attribute(ID::keep_hierarchy); - for (auto &tpl_name : celltypeMap.at(cell_type)) - if (map->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy)) - keepit = true; - if (keepit) { - if (!flatten_keep_list[cell]) { - log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell)); - flatten_keep_list.insert(cell); - } - if (!flatten_done_list[cell->type]) - flatten_do_list.insert(cell->type); - continue; + bool keepit = cell->get_bool_attribute(ID::keep_hierarchy); + for (auto &tpl_name : celltypeMap.at(cell_type)) + if (map->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy)) + keepit = true; + if (keepit) { + if (!flatten_keep_list[cell]) { + log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell)); + flatten_keep_list.insert(cell); } + if (!flatten_done_list[cell->type]) + flatten_do_list.insert(cell->type); + continue; } for (auto &conn : cell->connections()) @@ -548,7 +334,6 @@ struct TechmapWorker { log_assert(handled_cells.count(cell) == 0); log_assert(cell == module->cell(cell->name)); - bool mapped_cell = false; std::string cell_type = cell->type.str(); @@ -564,484 +349,41 @@ struct TechmapWorker if (tpl->get_blackbox_attribute(ignore_wb)) continue; - if (!flatten_mode) - { - std::string extmapper_name; - - if (tpl->get_bool_attribute(ID::techmap_simplemap)) - extmapper_name = "simplemap"; - - if (tpl->get_bool_attribute(ID::techmap_maccmap)) - extmapper_name = "maccmap"; - - if (tpl->attributes.count(ID::techmap_wrap)) - extmapper_name = "wrap"; - - if (!extmapper_name.empty()) - { - cell->type = cell_type; - - if ((extern_mode && !in_recursion) || extmapper_name == "wrap") - { - std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type)); - - for (auto &c : cell->parameters) - m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second)); - - if (extmapper_name == "wrap") - m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string()); - - RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design; - RTLIL::Module *extmapper_module = extmapper_design->module(m_name); - - if (extmapper_module == nullptr) - { - extmapper_module = extmapper_design->addModule(m_name); - RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell); - - extmapper_cell->set_src_attribute(cell->get_src_attribute()); - - int port_counter = 1; - for (auto &c : extmapper_cell->connections_) { - RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second)); - if (w->name.in(ID::Y, ID::Q)) - w->port_output = true; - else - w->port_input = true; - w->port_id = port_counter++; - c.second = w; - } - - extmapper_module->fixup_ports(); - extmapper_module->check(); - - if (extmapper_name == "simplemap") { - log("Creating %s with simplemap.\n", log_id(extmapper_module)); - if (simplemap_mappers.count(extmapper_cell->type) == 0) - log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type)); - simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell); - extmapper_module->remove(extmapper_cell); - } - - if (extmapper_name == "maccmap") { - log("Creating %s with maccmap.\n", log_id(extmapper_module)); - if (extmapper_cell->type != ID($macc)) - log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type)); - maccmap(extmapper_module, extmapper_cell); - extmapper_module->remove(extmapper_cell); - } - - if (extmapper_name == "wrap") { - std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string(); - log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module)); - mkdebug.on(); - Pass::call_on_module(extmapper_design, extmapper_module, cmd_string); - log_continue = true; - } - } - - cell->type = extmapper_module->name; - cell->parameters.clear(); - - if (!extern_mode || in_recursion) { - tpl = extmapper_module; - goto use_wrapper_tpl; - } - - auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type)); - if (!log_msg_cache.count(msg)) { - log_msg_cache.insert(msg); - log("%s\n", msg.c_str()); - } - log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module)); - } - else - { - auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type)); - if (!log_msg_cache.count(msg)) { - log_msg_cache.insert(msg); - log("%s\n", msg.c_str()); - } - log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str()); - - if (extmapper_name == "simplemap") { - if (simplemap_mappers.count(cell->type) == 0) - log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type)); - simplemap_mappers.at(cell->type)(module, cell); - } - - if (extmapper_name == "maccmap") { - if (cell->type != ID($macc)) - log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type)); - maccmap(module, cell); - } - - module->remove(cell); - cell = nullptr; - } - - did_something = true; - mapped_cell = true; - break; - } - - for (auto &conn : cell->connections()) { - if (conn.first.begins_with("$")) - continue; - if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0) - continue; - if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0) - goto next_tpl; - parameters[conn.first] = conn.second.as_const(); - } - - if (0) { - next_tpl: - continue; - } - - if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0) - parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type)); - - for (auto &conn : cell->connections()) { - if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) { - std::vector v = sigmap(conn.second).to_sigbit_vector(); - for (auto &bit : v) - bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0); - parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); - } - if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) { - std::vector v = sigmap(conn.second).to_sigbit_vector(); - for (auto &bit : v) - if (bit.wire != nullptr) - bit = RTLIL::SigBit(RTLIL::State::Sx); - parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); - } - if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) { - auto sig = sigmap(conn.second); - RTLIL::Const value(State::Sx, sig.size()); - for (int i = 0; i < sig.size(); i++) { - auto it = init_bits.find(sig[i]); - if (it != init_bits.end()) { - value[i] = it->second; - } - } - parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value); - } - } - - int unique_bit_id_counter = 0; - dict unique_bit_id; - unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++; - unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++; - unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++; - unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++; - - for (auto &conn : cell->connections()) - if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) { - for (auto &bit : sigmap(conn.second)) - if (unique_bit_id.count(bit) == 0) - unique_bit_id[bit] = unique_bit_id_counter++; - } - - // Find highest bit set - int bits = 0; - for (int i = 0; i < 32; i++) - if (((unique_bit_id_counter-1) & (1 << i)) != 0) - bits = i; - // Increment index by one to get number of bits - bits++; - if (tpl->avail_parameters.count(ID::_TECHMAP_BITS_CONNMAP_)) - parameters[ID::_TECHMAP_BITS_CONNMAP_] = bits; - - for (auto &conn : cell->connections()) - if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) { - RTLIL::Const value; - for (auto &bit : sigmap(conn.second)) { - int val = unique_bit_id.at(bit); - for (int i = 0; i < bits; i++) { - value.bits.push_back((val & 1) != 0 ? State::S1 : State::S0); - val = val >> 1; - } - } - parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), value); - } - } - - if (0) { - use_wrapper_tpl:; - // do not register techmap_wrap modules with techmap_cache + std::pair> key(tpl_name, parameters); + auto it = techmap_cache.find(key); + if (it != techmap_cache.end()) { + tpl = it->second; } else { - std::pair> key(tpl_name, parameters); - auto it = techmap_cache.find(key); - if (it != techmap_cache.end()) { - tpl = it->second; - } else { - if (parameters.size() != 0) { - mkdebug.on(); - derived_name = tpl->derive(map, parameters); - tpl = map->module(derived_name); - log_continue = true; - } - techmap_cache.emplace(std::move(key), tpl); + if (parameters.size() != 0) { + mkdebug.on(); + derived_name = tpl->derive(map, parameters); + tpl = map->module(derived_name); + log_continue = true; } + techmap_cache.emplace(std::move(key), tpl); } - if (flatten_mode) { - techmap_do_cache[tpl] = true; - } else { - RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false)); - if (constmapped_tpl != nullptr) - tpl = constmapped_tpl; - } - - if (techmap_do_cache.count(tpl) == 0) - { - bool keep_running = true; - techmap_do_cache[tpl] = true; - - pool techmap_wire_names; - - while (keep_running) - { - TechmapWires twd = techmap_find_special_wires(tpl); - keep_running = false; - - for (auto &it : twd) - techmap_wire_names.insert(it.first); - - for (auto &it : twd[ID::_TECHMAP_FAIL_]) { - RTLIL::SigSpec value = it.value; - if (value.is_fully_const() && value.as_bool()) { - log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n", - derived_name.c_str(), log_id(it.wire->name), log_signal(value)); - techmap_do_cache[tpl] = false; - } - } - - if (!techmap_do_cache[tpl]) - break; - - for (auto &it : twd) - { - if (!it.first.begins_with("\\_TECHMAP_DO_") || it.second.empty()) - continue; - - auto &data = it.second.front(); - - if (!data.value.is_fully_const()) - log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(data.wire->name), log_signal(data.value)); - - techmap_wire_names.erase(it.first); - - const char *p = data.wire->name.c_str(); - const char *q = strrchr(p+1, '.'); - q = q ? q : p+1; - - std::string cmd_string = data.value.as_const().decode_string(); - - restart_eval_cmd_string: - if (cmd_string.rfind("CONSTMAP; ", 0) == 0) - { - cmd_string = cmd_string.substr(strlen("CONSTMAP; ")); - - log("Analyzing pattern of constant bits for this cell:\n"); - IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true); - log("Creating constmapped module `%s'.\n", log_id(new_tpl_name)); - log_assert(map->module(new_tpl_name) == nullptr); - - RTLIL::Module *new_tpl = map->addModule(new_tpl_name); - tpl->cloneInto(new_tpl); - - techmap_do_cache.erase(tpl); - techmap_do_cache[new_tpl] = true; - tpl = new_tpl; - - dict port_new2old_map; - dict port_connmap; - dict cellbits_to_tplbits; - - for (auto wire : tpl->wires().to_vector()) - { - if (!wire->port_input || wire->port_output) - continue; - - IdString port_name = wire->name; - tpl->rename(wire, NEW_ID); - - RTLIL::Wire *new_wire = tpl->addWire(port_name, wire); - wire->port_input = false; - wire->port_id = 0; - - for (int i = 0; i < wire->width; i++) { - port_new2old_map.emplace(RTLIL::SigBit(new_wire, i), RTLIL::SigBit(wire, i)); - port_connmap.emplace(RTLIL::SigBit(wire, i), RTLIL::SigBit(new_wire, i)); - } - } - - for (auto &conn : cell->connections()) - for (int i = 0; i < GetSize(conn.second); i++) - { - RTLIL::SigBit bit = sigmap(conn.second[i]); - RTLIL::SigBit tplbit(tpl->wire(conn.first), i); - - if (bit.wire == nullptr) - { - RTLIL::SigBit oldbit = port_new2old_map.at(tplbit); - port_connmap.at(oldbit) = bit; - } - else if (cellbits_to_tplbits.count(bit)) - { - RTLIL::SigBit oldbit = port_new2old_map.at(tplbit); - port_connmap.at(oldbit) = cellbits_to_tplbits[bit]; - } - else - cellbits_to_tplbits[bit] = tplbit; - } - - RTLIL::SigSig port_conn; - for (auto &it : port_connmap) { - port_conn.first.append(it.first); - port_conn.second.append(it.second); - } - tpl->connect(port_conn); - - tpl->check(); - goto restart_eval_cmd_string; - } - - if (cmd_string.rfind("RECURSION; ", 0) == 0) - { - cmd_string = cmd_string.substr(strlen("RECURSION; ")); - while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { } - goto restart_eval_cmd_string; - } - - Pass::call_on_module(map, tpl, cmd_string); - - log_assert(!strncmp(q, "_TECHMAP_DO_", 12)); - std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12); - while (tpl->wire(new_name) != nullptr) - new_name += "_"; - tpl->rename(data.wire->name, new_name); - - keep_running = true; - break; - } - } - - TechmapWires twd = techmap_find_special_wires(tpl); - for (auto &it : twd) { - if (it.first != ID::_TECHMAP_FAIL_ && (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && !it.first.begins_with("\\_TECHMAP_DO_") && !it.first.begins_with("\\_TECHMAP_DONE_")) - log_error("Techmap yielded unknown config wire %s.\n", log_id(it.first)); - if (techmap_do_cache[tpl]) - for (auto &it2 : it.second) - if (!it2.value.is_fully_const()) - log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(it2.wire->name), log_signal(it2.value)); - techmap_wire_names.erase(it.first); - } - - for (auto &it : techmap_wire_names) - log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", log_id(it)); - - if (recursive_mode) { - if (log_continue) { - log_header(design, "Continuing TECHMAP pass.\n"); - log_continue = false; - mkdebug.off(); - } - while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { } - } - } - - if (techmap_do_cache.at(tpl) == false) - continue; - if (log_continue) { log_header(design, "Continuing TECHMAP pass.\n"); log_continue = false; mkdebug.off(); } - TechmapWires twd = techmap_find_special_wires(tpl); - for (auto &it : twd) { - if (it.first.begins_with("\\_TECHMAP_REMOVEINIT_")) { - for (auto &it2 : it.second) { - auto val = it2.value.as_const(); - auto wirename = RTLIL::escape_id(it.first.substr(21, it.first.size() - 21 - 1)); - auto it = cell->connections().find(wirename); - if (it != cell->connections().end()) { - auto sig = sigmap(it->second); - for (int i = 0; i < sig.size(); i++) - if (val[i] == State::S1) - remove_init_bits.insert(sig[i]); - } - } - } - } - - if (extern_mode && !in_recursion) - { - std::string m_name = stringf("$extern:%s", log_id(tpl)); - - if (!design->module(m_name)) - { - RTLIL::Module *m = design->addModule(m_name); - tpl->cloneInto(m); - - for (auto cell : m->cells()) { - if (cell->type.begins_with("\\$")) - cell->type = cell->type.substr(1); - } - - module_queue.insert(m); - } - - log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name)); - cell->type = m_name; - cell->parameters.clear(); - } - else - { - auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type)); - if (!log_msg_cache.count(msg)) { - log_msg_cache.insert(msg); - log("%s\n", msg.c_str()); - } - log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); - techmap_module_worker(design, module, cell, tpl); - cell = nullptr; + auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type)); + if (!log_msg_cache.count(msg)) { + log_msg_cache.insert(msg); + log("%s\n", msg.c_str()); } + log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); + techmap_module_worker(design, module, cell, tpl); + cell = nullptr; did_something = true; - mapped_cell = true; break; } - if (assert_mode && !mapped_cell) - log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); - handled_cells.insert(cell); } - if (!remove_init_bits.empty()) { - for (auto wire : module->wires()) - if (wire->attributes.count(ID::init)) { - Const &value = wire->attributes.at(ID::init); - bool do_cleanup = true; - for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) { - SigBit bit = sigmap(SigBit(wire, i)); - if (remove_init_bits.count(bit)) - value[i] = State::Sx; - else if (value[i] != State::Sx) - do_cleanup = false; - } - if (do_cleanup) { - log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire)); - wire->attributes.erase(ID::init); - } - } - } - if (log_continue) { log_header(design, "Continuing TECHMAP pass.\n"); log_continue = false; @@ -1077,7 +419,6 @@ struct FlattenPass : public Pass { log_push(); TechmapWorker worker; - worker.flatten_mode = true; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 8659d0f36..9c0402e0f 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -67,10 +67,6 @@ struct TechmapWorker pool module_queue; dict sigmaps; - pool flatten_do_list; - pool flatten_done_list; - pool flatten_keep_list; - pool log_msg_cache; struct TechmapWireData { @@ -82,7 +78,6 @@ struct TechmapWorker bool extern_mode = false; bool assert_mode = false; - bool flatten_mode = false; bool recursive_mode = false; bool autoproc_mode = false; bool ignore_wb = false; @@ -168,13 +163,11 @@ struct TechmapWorker pool extra_src_attrs = cell->get_strpool_attribute(ID::src); orig_cell_name = cell->name.str(); - if (!flatten_mode) { - for (auto tpl_cell : tpl->cells()) - if (tpl_cell->name == ID::_TECHMAP_REPLACE_) { - module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str()); - break; - } - } + for (auto tpl_cell : tpl->cells()) + if (tpl_cell->name == ID::_TECHMAP_REPLACE_) { + module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str()); + break; + } dict memory_renames; @@ -205,7 +198,7 @@ struct TechmapWorker IdString posportname = stringf("$%d", tpl_w->port_id); positional_ports.emplace(posportname, tpl_w->name); - if (!flatten_mode && tpl_w->get_bool_attribute(ID::techmap_autopurge) && + if (tpl_w->get_bool_attribute(ID::techmap_autopurge) && (!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) && (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname)))) { @@ -221,26 +214,16 @@ struct TechmapWorker apply_prefix(cell->name, w_name); RTLIL::Wire *w = module->wire(w_name); if (w != nullptr) { - if (!flatten_mode || !w->get_bool_attribute(ID::hierconn)) { - temp_renamed_wires[w] = w->name; - module->rename(w, NEW_ID); - w = nullptr; - } else { - w->attributes.erase(ID::hierconn); - if (GetSize(w) < GetSize(tpl_w)) { - log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w), - log_id(tpl), log_id(tpl_w), log_id(module), log_id(cell)); - w->width = GetSize(tpl_w); - } - } + temp_renamed_wires[w] = w->name; + module->rename(w, NEW_ID); + w = nullptr; } if (w == nullptr) { w = module->addWire(w_name, tpl_w); w->port_input = false; w->port_output = false; w->port_id = 0; - if (!flatten_mode) - w->attributes.erase(ID::techmap_autopurge); + w->attributes.erase(ID::techmap_autopurge); if (tpl_w->get_bool_attribute(ID::_techmap_special_)) w->attributes.clear(); if (w->attributes.count(ID::src)) @@ -322,56 +305,37 @@ struct TechmapWorker log_assert(c.first.size() == c.second.size()); - if (flatten_mode) - { - // more conservative approach: - // connect internal and external wires - - if (sigmaps.count(module) == 0) - sigmaps[module].set(module); - - if (sigmaps.at(module)(c.first).has_const()) - log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n", - log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second)); + // replace internal wires that are connected to external wires + if (w->port_output && !w->port_input) { + port_signal_map.add(c.second, c.first); + } else + if (!w->port_output && w->port_input) { + port_signal_map.add(c.first, c.second); + } else { module->connect(c); + extra_connect = SigSig(); } - else - { - // approach that yields nicer outputs: - // replace internal wires that are connected to external wires - if (w->port_output && !w->port_input) { - port_signal_map.add(c.second, c.first); - } else - if (!w->port_output && w->port_input) { - port_signal_map.add(c.first, c.second); - } else { - module->connect(c); - extra_connect = SigSig(); - } - - for (auto &attr : w->attributes) { - if (attr.first == ID::src) - continue; - auto lhs = GetSize(extra_connect.first); - auto rhs = GetSize(extra_connect.second); - if (lhs > rhs) - extra_connect.first.remove(rhs, lhs-rhs); - else if (rhs > lhs) - extra_connect.second.remove(lhs, rhs-lhs); - module->connect(extra_connect); - break; - } + for (auto &attr : w->attributes) { + if (attr.first == ID::src) + continue; + auto lhs = GetSize(extra_connect.first); + auto rhs = GetSize(extra_connect.second); + if (lhs > rhs) + extra_connect.first.remove(rhs, lhs-rhs); + else if (rhs > lhs) + extra_connect.second.remove(lhs, rhs-lhs); + module->connect(extra_connect); + break; } } for (auto tpl_cell : tpl->cells()) { IdString c_name = tpl_cell->name; - bool techmap_replace_cell = (!flatten_mode) && (c_name == ID::_TECHMAP_REPLACE_); - if (techmap_replace_cell) + if (c_name == ID::_TECHMAP_REPLACE_) c_name = orig_cell_name; else if (tpl_cell->name.begins_with("\\_TECHMAP_REPLACE_.")) c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_")); @@ -381,7 +345,7 @@ struct TechmapWorker RTLIL::Cell *c = module->addCell(c_name, tpl_cell); design->select(module, c); - if (!flatten_mode && c->type.begins_with("\\$")) + if (c->type.begins_with("\\$")) c->type = c->type.substr(1); vector autopurge_ports; @@ -426,7 +390,7 @@ struct TechmapWorker if (c->attributes.count(ID::src)) c->add_strpool_attribute(ID::src, extra_src_attrs); - if (techmap_replace_cell) + if (c_name == ID::_TECHMAP_REPLACE_) for (auto attr : cell->attributes) if (!c->attributes.count(attr.first)) c->attributes[attr.first] = attr.second; @@ -499,22 +463,6 @@ struct TechmapWorker continue; } - if (flatten_mode) { - bool keepit = cell->get_bool_attribute(ID::keep_hierarchy); - for (auto &tpl_name : celltypeMap.at(cell_type)) - if (map->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy)) - keepit = true; - if (keepit) { - if (!flatten_keep_list[cell]) { - log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell)); - flatten_keep_list.insert(cell); - } - if (!flatten_done_list[cell->type]) - flatten_do_list.insert(cell->type); - continue; - } - } - for (auto &conn : cell->connections()) { RTLIL::SigSpec sig = sigmap(conn.second); @@ -564,172 +512,171 @@ struct TechmapWorker if (tpl->get_blackbox_attribute(ignore_wb)) continue; - if (!flatten_mode) + std::string extmapper_name; + + if (tpl->get_bool_attribute(ID::techmap_simplemap)) + extmapper_name = "simplemap"; + + if (tpl->get_bool_attribute(ID::techmap_maccmap)) + extmapper_name = "maccmap"; + + if (tpl->attributes.count(ID::techmap_wrap)) + extmapper_name = "wrap"; + + if (!extmapper_name.empty()) { - std::string extmapper_name; + cell->type = cell_type; - if (tpl->get_bool_attribute(ID::techmap_simplemap)) - extmapper_name = "simplemap"; - - if (tpl->get_bool_attribute(ID::techmap_maccmap)) - extmapper_name = "maccmap"; - - if (tpl->attributes.count(ID::techmap_wrap)) - extmapper_name = "wrap"; - - if (!extmapper_name.empty()) + if ((extern_mode && !in_recursion) || extmapper_name == "wrap") { - cell->type = cell_type; + std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type)); - if ((extern_mode && !in_recursion) || extmapper_name == "wrap") + for (auto &c : cell->parameters) + m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second)); + + if (extmapper_name == "wrap") + m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string()); + + RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design; + RTLIL::Module *extmapper_module = extmapper_design->module(m_name); + + if (extmapper_module == nullptr) { - std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type)); + extmapper_module = extmapper_design->addModule(m_name); + RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell); - for (auto &c : cell->parameters) - m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second)); + extmapper_cell->set_src_attribute(cell->get_src_attribute()); - if (extmapper_name == "wrap") - m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string()); - - RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design; - RTLIL::Module *extmapper_module = extmapper_design->module(m_name); - - if (extmapper_module == nullptr) - { - extmapper_module = extmapper_design->addModule(m_name); - RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell); - - extmapper_cell->set_src_attribute(cell->get_src_attribute()); - - int port_counter = 1; - for (auto &c : extmapper_cell->connections_) { - RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second)); - if (w->name.in(ID::Y, ID::Q)) - w->port_output = true; - else - w->port_input = true; - w->port_id = port_counter++; - c.second = w; - } - - extmapper_module->fixup_ports(); - extmapper_module->check(); - - if (extmapper_name == "simplemap") { - log("Creating %s with simplemap.\n", log_id(extmapper_module)); - if (simplemap_mappers.count(extmapper_cell->type) == 0) - log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type)); - simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell); - extmapper_module->remove(extmapper_cell); - } - - if (extmapper_name == "maccmap") { - log("Creating %s with maccmap.\n", log_id(extmapper_module)); - if (extmapper_cell->type != ID($macc)) - log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type)); - maccmap(extmapper_module, extmapper_cell); - extmapper_module->remove(extmapper_cell); - } - - if (extmapper_name == "wrap") { - std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string(); - log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module)); - mkdebug.on(); - Pass::call_on_module(extmapper_design, extmapper_module, cmd_string); - log_continue = true; - } + int port_counter = 1; + for (auto &c : extmapper_cell->connections_) { + RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second)); + if (w->name.in(ID::Y, ID::Q)) + w->port_output = true; + else + w->port_input = true; + w->port_id = port_counter++; + c.second = w; } - cell->type = extmapper_module->name; - cell->parameters.clear(); - - if (!extern_mode || in_recursion) { - tpl = extmapper_module; - goto use_wrapper_tpl; - } - - auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type)); - if (!log_msg_cache.count(msg)) { - log_msg_cache.insert(msg); - log("%s\n", msg.c_str()); - } - log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module)); - } - else - { - auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type)); - if (!log_msg_cache.count(msg)) { - log_msg_cache.insert(msg); - log("%s\n", msg.c_str()); - } - log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str()); + extmapper_module->fixup_ports(); + extmapper_module->check(); if (extmapper_name == "simplemap") { - if (simplemap_mappers.count(cell->type) == 0) - log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type)); - simplemap_mappers.at(cell->type)(module, cell); + log("Creating %s with simplemap.\n", log_id(extmapper_module)); + if (simplemap_mappers.count(extmapper_cell->type) == 0) + log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type)); + simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell); + extmapper_module->remove(extmapper_cell); } if (extmapper_name == "maccmap") { - if (cell->type != ID($macc)) - log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type)); - maccmap(module, cell); + log("Creating %s with maccmap.\n", log_id(extmapper_module)); + if (extmapper_cell->type != ID($macc)) + log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type)); + maccmap(extmapper_module, extmapper_cell); + extmapper_module->remove(extmapper_cell); } - module->remove(cell); - cell = nullptr; + if (extmapper_name == "wrap") { + std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string(); + log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module)); + mkdebug.on(); + Pass::call_on_module(extmapper_design, extmapper_module, cmd_string); + log_continue = true; + } } - did_something = true; - mapped_cell = true; - break; + cell->type = extmapper_module->name; + cell->parameters.clear(); + + if (!extern_mode || in_recursion) { + tpl = extmapper_module; + goto use_wrapper_tpl; + } + + auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type)); + if (!log_msg_cache.count(msg)) { + log_msg_cache.insert(msg); + log("%s\n", msg.c_str()); + } + log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module)); + } + else + { + auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type)); + if (!log_msg_cache.count(msg)) { + log_msg_cache.insert(msg); + log("%s\n", msg.c_str()); + } + log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str()); + + if (extmapper_name == "simplemap") { + if (simplemap_mappers.count(cell->type) == 0) + log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type)); + simplemap_mappers.at(cell->type)(module, cell); + } + + if (extmapper_name == "maccmap") { + if (cell->type != ID($macc)) + log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type)); + maccmap(module, cell); + } + + module->remove(cell); + cell = nullptr; } - for (auto &conn : cell->connections()) { - if (conn.first.begins_with("$")) - continue; - if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0) - continue; - if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0) - goto next_tpl; - parameters[conn.first] = conn.second.as_const(); - } + did_something = true; + mapped_cell = true; + break; + } - if (0) { - next_tpl: + for (auto &conn : cell->connections()) { + if (conn.first.begins_with("$")) continue; + if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0) + continue; + if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0) + goto next_tpl; + parameters[conn.first] = conn.second.as_const(); + } + + if (0) { + next_tpl: + continue; + } + + if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0) + parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type)); + + for (auto &conn : cell->connections()) { + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) { + std::vector v = sigmap(conn.second).to_sigbit_vector(); + for (auto &bit : v) + bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0); + parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); } - - if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0) - parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type)); - - for (auto &conn : cell->connections()) { - if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) { - std::vector v = sigmap(conn.second).to_sigbit_vector(); - for (auto &bit : v) - bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0); - parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); - } - if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) { - std::vector v = sigmap(conn.second).to_sigbit_vector(); - for (auto &bit : v) - if (bit.wire != nullptr) - bit = RTLIL::SigBit(RTLIL::State::Sx); - parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); - } - if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) { - auto sig = sigmap(conn.second); - RTLIL::Const value(State::Sx, sig.size()); - for (int i = 0; i < sig.size(); i++) { - auto it = init_bits.find(sig[i]); - if (it != init_bits.end()) { - value[i] = it->second; - } + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) { + std::vector v = sigmap(conn.second).to_sigbit_vector(); + for (auto &bit : v) + if (bit.wire != nullptr) + bit = RTLIL::SigBit(RTLIL::State::Sx); + parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); + } + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) { + auto sig = sigmap(conn.second); + RTLIL::Const value(State::Sx, sig.size()); + for (int i = 0; i < sig.size(); i++) { + auto it = init_bits.find(sig[i]); + if (it != init_bits.end()) { + value[i] = it->second; } - parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value); } + parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value); } + } + { int unique_bit_id_counter = 0; dict unique_bit_id; unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++; @@ -787,13 +734,9 @@ struct TechmapWorker } } - if (flatten_mode) { - techmap_do_cache[tpl] = true; - } else { - RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false)); - if (constmapped_tpl != nullptr) - tpl = constmapped_tpl; - } + RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false)); + if (constmapped_tpl != nullptr) + tpl = constmapped_tpl; if (techmap_do_cache.count(tpl) == 0) { From ebbbe2156e9c5f2d04964840974c915ba8500159 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 3 Jun 2020 00:51:42 +0000 Subject: [PATCH 03/13] flatten: rename techmap-related stuff. NFC. --- passes/techmap/flatten.cc | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index 214cda844..605759bec 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -33,7 +33,7 @@ void apply_prefix(IdString prefix, IdString &id) if (id[0] == '\\') id = stringf("%s.%s", prefix.c_str(), id.c_str()+1); else - id = stringf("$techmap%s.%s", prefix.c_str(), id.c_str()); + id = stringf("$flatten%s.%s", prefix.c_str(), id.c_str()); } void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) @@ -49,9 +49,9 @@ void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) sig = chunks; } -struct TechmapWorker +struct FlattenWorker { - dict>, RTLIL::Module*> techmap_cache; + dict>, RTLIL::Module*> cache; dict sigmaps; pool flatten_do_list; @@ -62,14 +62,14 @@ struct TechmapWorker bool ignore_wb = false; - void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl) + void flatten_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl) { if (tpl->processes.size() != 0) { - log("Technology map yielded processes:"); + log("Flattening yielded processes:"); for (auto &it : tpl->processes) log(" %s",log_id(it.first)); log("\n"); - log_error("Technology map yielded processes -> this is not supported.\n"); + log_error("Flattening yielded processes -> this is not supported.\n"); } pool extra_src_attrs = cell->get_strpool_attribute(ID::src); @@ -257,7 +257,7 @@ struct TechmapWorker } } - bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool &handled_cells, + bool flatten_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool &handled_cells, const dict> &celltypeMap, bool in_recursion) { std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; @@ -350,8 +350,8 @@ struct TechmapWorker continue; std::pair> key(tpl_name, parameters); - auto it = techmap_cache.find(key); - if (it != techmap_cache.end()) { + auto it = cache.find(key); + if (it != cache.end()) { tpl = it->second; } else { if (parameters.size() != 0) { @@ -360,11 +360,11 @@ struct TechmapWorker tpl = map->module(derived_name); log_continue = true; } - techmap_cache.emplace(std::move(key), tpl); + cache.emplace(std::move(key), tpl); } if (log_continue) { - log_header(design, "Continuing TECHMAP pass.\n"); + log_header(design, "Continuing FLATTEN pass.\n"); log_continue = false; mkdebug.off(); } @@ -375,7 +375,7 @@ struct TechmapWorker log("%s\n", msg.c_str()); } log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); - techmap_module_worker(design, module, cell, tpl); + flatten_module(design, module, cell, tpl); cell = nullptr; did_something = true; break; @@ -385,7 +385,7 @@ struct TechmapWorker } if (log_continue) { - log_header(design, "Continuing TECHMAP pass.\n"); + log_header(design, "Continuing FLATTEN pass.\n"); log_continue = false; mkdebug.off(); } @@ -418,7 +418,7 @@ struct FlattenPass : public Pass { log_header(design, "Executing FLATTEN pass (flatten design).\n"); log_push(); - TechmapWorker worker; + FlattenWorker worker; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -448,13 +448,13 @@ struct FlattenPass : public Pass { worker.flatten_do_list.insert(top_mod->name); while (!worker.flatten_do_list.empty()) { auto mod = design->module(*worker.flatten_do_list.begin()); - while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { } + while (worker.flatten_module(design, mod, design, handled_cells, celltypeMap, false)) { } worker.flatten_done_list.insert(mod->name); worker.flatten_do_list.erase(mod->name); } } else { for (auto mod : design->modules().to_vector()) - while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { } + while (worker.flatten_module(design, mod, design, handled_cells, celltypeMap, false)) { } } log_suppressed(); From 9338ff66b9fb86f3485f060b04f4e4b8a1fc18f6 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 3 Jun 2020 14:35:27 +0000 Subject: [PATCH 04/13] RTLIL: factor out RTLIL::Module::addMemory. NFC. --- kernel/rtlil.cc | 12 ++++++++++++ kernel/rtlil.h | 2 ++ passes/techmap/flatten.cc | 8 +------- passes/techmap/techmap.cc | 8 +------- 4 files changed, 16 insertions(+), 14 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ca4201b53..dc1add0ff 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1884,6 +1884,18 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth return cell; } +RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other) +{ + RTLIL::Memory *mem = new RTLIL::Memory; + mem->name = name; + mem->width = other->width; + mem->start_offset = other->start_offset; + mem->size = other->size; + mem->attributes = other->attributes; + memories[mem->name] = mem; + return mem; +} + #define DEF_METHOD(_func, _y_size, _type) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 8228523d5..8d2e42b42 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1170,6 +1170,8 @@ public: RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); + RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other); + // The add* methods create a cell and return the created cell. All signals must exist in advance. RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index 605759bec..dbea12dca 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -79,15 +79,9 @@ struct FlattenWorker for (auto &it : tpl->memories) { IdString m_name = it.first; apply_prefix(cell->name, m_name); - RTLIL::Memory *m = new RTLIL::Memory; - m->name = m_name; - m->width = it.second->width; - m->start_offset = it.second->start_offset; - m->size = it.second->size; - m->attributes = it.second->attributes; + RTLIL::Memory *m = module->addMemory(m_name, it.second); if (m->attributes.count(ID::src)) m->add_strpool_attribute(ID::src, extra_src_attrs); - module->memories[m->name] = m; memory_renames[it.first] = m->name; design->select(module, m); } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 9c0402e0f..535db9465 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -174,15 +174,9 @@ struct TechmapWorker for (auto &it : tpl->memories) { IdString m_name = it.first; apply_prefix(cell->name, m_name); - RTLIL::Memory *m = new RTLIL::Memory; - m->name = m_name; - m->width = it.second->width; - m->start_offset = it.second->start_offset; - m->size = it.second->size; - m->attributes = it.second->attributes; + RTLIL::Memory *m = module->addMemory(m_name, it.second); if (m->attributes.count(ID::src)) m->add_strpool_attribute(ID::src, extra_src_attrs); - module->memories[m->name] = m; memory_renames[it.first] = m->name; design->select(module, m); } From 6783876807a4ef9e910bd30b1fbafa44911cac66 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 3 Jun 2020 01:19:55 +0000 Subject: [PATCH 05/13] flatten: simplify. NFC. The `design` and `map` designs are always the same when flattening. --- passes/techmap/flatten.cc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index dbea12dca..c5014bbc0 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -251,7 +251,7 @@ struct FlattenWorker } } - bool flatten_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool &handled_cells, + bool flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool &handled_cells, const dict> &celltypeMap, bool in_recursion) { std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; @@ -283,7 +283,7 @@ struct FlattenWorker bool keepit = cell->get_bool_attribute(ID::keep_hierarchy); for (auto &tpl_name : celltypeMap.at(cell_type)) - if (map->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy)) + if (design->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy)) keepit = true; if (keepit) { if (!flatten_keep_list[cell]) { @@ -304,7 +304,7 @@ struct FlattenWorker continue; for (auto &tpl_name : celltypeMap.at(cell_type)) { - RTLIL::Module *tpl = map->module(tpl_name); + RTLIL::Module *tpl = design->module(tpl_name); RTLIL::Wire *port = tpl->wire(conn.first); if (port && port->port_input) cell_to_inbit[cell].insert(sig.begin(), sig.end()); @@ -337,7 +337,7 @@ struct FlattenWorker for (auto &tpl_name : celltypeMap.at(cell_type)) { IdString derived_name = tpl_name; - RTLIL::Module *tpl = map->module(tpl_name); + RTLIL::Module *tpl = design->module(tpl_name); dict parameters(cell->parameters); if (tpl->get_blackbox_attribute(ignore_wb)) @@ -350,8 +350,8 @@ struct FlattenWorker } else { if (parameters.size() != 0) { mkdebug.on(); - derived_name = tpl->derive(map, parameters); - tpl = map->module(derived_name); + derived_name = tpl->derive(design, parameters); + tpl = design->module(derived_name); log_continue = true; } cache.emplace(std::move(key), tpl); @@ -442,13 +442,13 @@ struct FlattenPass : public Pass { worker.flatten_do_list.insert(top_mod->name); while (!worker.flatten_do_list.empty()) { auto mod = design->module(*worker.flatten_do_list.begin()); - while (worker.flatten_module(design, mod, design, handled_cells, celltypeMap, false)) { } + while (worker.flatten_module(design, mod, handled_cells, celltypeMap, false)) { } worker.flatten_done_list.insert(mod->name); worker.flatten_do_list.erase(mod->name); } } else { for (auto mod : design->modules().to_vector()) - while (worker.flatten_module(design, mod, design, handled_cells, celltypeMap, false)) { } + while (worker.flatten_module(design, mod, handled_cells, celltypeMap, false)) { } } log_suppressed(); From e561a3a76f392416ded61d9aeb830164476ae507 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 3 Jun 2020 02:09:09 +0000 Subject: [PATCH 06/13] flatten: simplify. NFC. The `celltypeMap` always maps `x` to `{x}`. --- passes/techmap/flatten.cc | 118 ++++++++++++++------------------------ 1 file changed, 42 insertions(+), 76 deletions(-) diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index c5014bbc0..beb77b52d 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -58,8 +58,6 @@ struct FlattenWorker pool flatten_done_list; pool flatten_keep_list; - pool log_msg_cache; - bool ignore_wb = false; void flatten_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl) @@ -251,8 +249,7 @@ struct FlattenWorker } } - bool flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool &handled_cells, - const dict> &celltypeMap, bool in_recursion) + bool flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool &handled_cells, bool in_recursion) { std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; @@ -274,18 +271,10 @@ struct FlattenWorker if (handled_cells.count(cell) > 0) continue; - std::string cell_type = cell->type.str(); - if (in_recursion && cell->type.begins_with("\\$")) - cell_type = cell_type.substr(1); - - if (celltypeMap.count(cell_type) == 0) + if (!design->has(cell->type)) continue; - bool keepit = cell->get_bool_attribute(ID::keep_hierarchy); - for (auto &tpl_name : celltypeMap.at(cell_type)) - if (design->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy)) - keepit = true; - if (keepit) { + if (cell->get_bool_attribute(ID::keep_hierarchy) || design->module(cell->type)->get_bool_attribute(ID::keep_hierarchy)) { if (!flatten_keep_list[cell]) { log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell)); flatten_keep_list.insert(cell); @@ -303,15 +292,13 @@ struct FlattenWorker if (GetSize(sig) == 0) continue; - for (auto &tpl_name : celltypeMap.at(cell_type)) { - RTLIL::Module *tpl = design->module(tpl_name); - RTLIL::Wire *port = tpl->wire(conn.first); - if (port && port->port_input) - cell_to_inbit[cell].insert(sig.begin(), sig.end()); - if (port && port->port_output) - for (auto &bit : sig) - outbit_to_cell[bit].insert(cell); - } + RTLIL::Module *tpl = design->module(cell->type); + RTLIL::Wire *port = tpl->wire(conn.first); + if (port && port->port_input) + cell_to_inbit[cell].insert(sig.begin(), sig.end()); + if (port && port->port_output) + for (auto &bit : sig) + outbit_to_cell[bit].insert(cell); } cells.node(cell); @@ -329,53 +316,39 @@ struct FlattenWorker log_assert(handled_cells.count(cell) == 0); log_assert(cell == module->cell(cell->name)); - std::string cell_type = cell->type.str(); + RTLIL::Module *tpl = design->module(cell->type); + dict parameters(cell->parameters); - if (in_recursion && cell->type.begins_with("\\$")) - cell_type = cell_type.substr(1); - - for (auto &tpl_name : celltypeMap.at(cell_type)) - { - IdString derived_name = tpl_name; - RTLIL::Module *tpl = design->module(tpl_name); - dict parameters(cell->parameters); - - if (tpl->get_blackbox_attribute(ignore_wb)) - continue; - - std::pair> key(tpl_name, parameters); - auto it = cache.find(key); - if (it != cache.end()) { - tpl = it->second; - } else { - if (parameters.size() != 0) { - mkdebug.on(); - derived_name = tpl->derive(design, parameters); - tpl = design->module(derived_name); - log_continue = true; - } - cache.emplace(std::move(key), tpl); - } - - if (log_continue) { - log_header(design, "Continuing FLATTEN pass.\n"); - log_continue = false; - mkdebug.off(); - } - - auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type)); - if (!log_msg_cache.count(msg)) { - log_msg_cache.insert(msg); - log("%s\n", msg.c_str()); - } - log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); - flatten_module(design, module, cell, tpl); - cell = nullptr; - did_something = true; - break; + if (tpl->get_blackbox_attribute(ignore_wb)) { + handled_cells.insert(cell); + continue; } - handled_cells.insert(cell); + std::pair> key(cell->type, parameters); + IdString derived_name; + auto it = cache.find(key); + if (it != cache.end()) { + derived_name = cell->type; + tpl = it->second; + } else { + if (parameters.size() != 0) { + mkdebug.on(); + derived_name = tpl->derive(design, parameters); + tpl = design->module(derived_name); + log_continue = true; + } + cache.emplace(std::move(key), tpl); + } + + if (log_continue) { + log_header(design, "Continuing FLATTEN pass.\n"); + log_continue = false; + mkdebug.off(); + } + + log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); + flatten_module(design, module, cell, tpl); + did_something = true; } if (log_continue) { @@ -424,13 +397,6 @@ struct FlattenPass : public Pass { } extra_args(args, argidx, design); - - dict> celltypeMap; - for (auto module : design->modules()) - celltypeMap[module->name].insert(module->name); - for (auto &i : celltypeMap) - i.second.sort(RTLIL::sort_by_id_str()); - RTLIL::Module *top_mod = nullptr; if (design->full_selection()) for (auto mod : design->modules()) @@ -442,13 +408,13 @@ struct FlattenPass : public Pass { worker.flatten_do_list.insert(top_mod->name); while (!worker.flatten_do_list.empty()) { auto mod = design->module(*worker.flatten_do_list.begin()); - while (worker.flatten_module(design, mod, handled_cells, celltypeMap, false)) { } + while (worker.flatten_module(design, mod, handled_cells, false)) { } worker.flatten_done_list.insert(mod->name); worker.flatten_do_list.erase(mod->name); } } else { for (auto mod : design->modules().to_vector()) - while (worker.flatten_module(design, mod, handled_cells, celltypeMap, false)) { } + while (worker.flatten_module(design, mod, handled_cells, false)) { } } log_suppressed(); From 3c3fa774e583af93e2713347b7840ef5d70d3a31 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 3 Jun 2020 02:11:04 +0000 Subject: [PATCH 07/13] flatten: simplify. NFC. Flattening always does "non-recursive" mapping. --- passes/techmap/flatten.cc | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index beb77b52d..94b2f387a 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -249,10 +249,8 @@ struct FlattenWorker } } - bool flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool &handled_cells, bool in_recursion) + bool flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool &handled_cells) { - std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; - if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb)) return false; @@ -346,7 +344,7 @@ struct FlattenWorker mkdebug.off(); } - log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); + log_debug("Flattening %s.%s (%s) using %s.\n", log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); flatten_module(design, module, cell, tpl); did_something = true; } @@ -408,13 +406,13 @@ struct FlattenPass : public Pass { worker.flatten_do_list.insert(top_mod->name); while (!worker.flatten_do_list.empty()) { auto mod = design->module(*worker.flatten_do_list.begin()); - while (worker.flatten_module(design, mod, handled_cells, false)) { } + while (worker.flatten_module(design, mod, handled_cells)) { } worker.flatten_done_list.insert(mod->name); worker.flatten_do_list.erase(mod->name); } } else { for (auto mod : design->modules().to_vector()) - while (worker.flatten_module(design, mod, handled_cells, false)) { } + while (worker.flatten_module(design, mod, handled_cells)) { } } log_suppressed(); From 5d2b6d1394f504729c0f2670b87534ea7efaec4b Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 3 Jun 2020 02:28:39 +0000 Subject: [PATCH 08/13] flatten: simplify. NFC. Flatten is non-recursive and doesn't need to keep track of handled cells. --- passes/techmap/flatten.cc | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index 94b2f387a..f37be685b 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -249,7 +249,7 @@ struct FlattenWorker } } - bool flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool &handled_cells) + bool flatten_module(RTLIL::Design *design, RTLIL::Module *module) { if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb)) return false; @@ -266,9 +266,6 @@ struct FlattenWorker for (auto cell : module->selected_cells()) { - if (handled_cells.count(cell) > 0) - continue; - if (!design->has(cell->type)) continue; @@ -311,16 +308,13 @@ struct FlattenWorker for (auto cell : cells.sorted) { - log_assert(handled_cells.count(cell) == 0); log_assert(cell == module->cell(cell->name)); RTLIL::Module *tpl = design->module(cell->type); dict parameters(cell->parameters); - if (tpl->get_blackbox_attribute(ignore_wb)) { - handled_cells.insert(cell); + if (tpl->get_blackbox_attribute(ignore_wb)) continue; - } std::pair> key(cell->type, parameters); IdString derived_name; @@ -401,18 +395,17 @@ struct FlattenPass : public Pass { if (mod->get_bool_attribute(ID::top)) top_mod = mod; - pool handled_cells; if (top_mod != nullptr) { worker.flatten_do_list.insert(top_mod->name); while (!worker.flatten_do_list.empty()) { auto mod = design->module(*worker.flatten_do_list.begin()); - while (worker.flatten_module(design, mod, handled_cells)) { } + while (worker.flatten_module(design, mod)) { } worker.flatten_done_list.insert(mod->name); worker.flatten_do_list.erase(mod->name); } } else { for (auto mod : design->modules().to_vector()) - while (worker.flatten_module(design, mod, handled_cells)) { } + while (worker.flatten_module(design, mod)) { } } log_suppressed(); From 66255dab4ef3f7257aec65bbbf5b1901f2ee1ebd Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 3 Jun 2020 16:00:40 +0000 Subject: [PATCH 09/13] flatten: simplify. Flattening does not benefit from topologically sorting cells within a module when processing them. --- passes/techmap/flatten.cc | 35 ----------------------------------- 1 file changed, 35 deletions(-) diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index f37be685b..82e697495 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -260,10 +260,6 @@ struct FlattenWorker SigMap sigmap(module); - TopoSort> cells; - dict> cell_to_inbit; - dict> outbit_to_cell; - for (auto cell : module->selected_cells()) { if (!design->has(cell->type)) @@ -279,37 +275,6 @@ struct FlattenWorker continue; } - for (auto &conn : cell->connections()) - { - RTLIL::SigSpec sig = sigmap(conn.second); - sig.remove_const(); - - if (GetSize(sig) == 0) - continue; - - RTLIL::Module *tpl = design->module(cell->type); - RTLIL::Wire *port = tpl->wire(conn.first); - if (port && port->port_input) - cell_to_inbit[cell].insert(sig.begin(), sig.end()); - if (port && port->port_output) - for (auto &bit : sig) - outbit_to_cell[bit].insert(cell); - } - - cells.node(cell); - } - - for (auto &it_right : cell_to_inbit) - for (auto &it_sigbit : it_right.second) - for (auto &it_left : outbit_to_cell[it_sigbit]) - cells.edge(it_left, it_right.first); - - cells.sort(); - - for (auto cell : cells.sorted) - { - log_assert(cell == module->cell(cell->name)); - RTLIL::Module *tpl = design->module(cell->type); dict parameters(cell->parameters); From d3e21003060a6395089a21ea2f81a7a689eb1884 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 3 Jun 2020 16:25:46 +0000 Subject: [PATCH 10/13] flatten: simplify. NFC. Remove redundant sigmaps. --- passes/techmap/flatten.cc | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index 82e697495..75345fcc1 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -52,7 +52,6 @@ void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) struct FlattenWorker { dict>, RTLIL::Module*> cache; - dict sigmaps; pool flatten_do_list; pool flatten_done_list; @@ -122,6 +121,8 @@ struct FlattenWorker design->select(module, w); } + SigMap sigmap(module); + SigMap tpl_sigmap(tpl); pool tpl_written_bits; @@ -185,10 +186,7 @@ struct FlattenWorker // connect internal and external wires - if (sigmaps.count(module) == 0) - sigmaps[module].set(module); - - if (sigmaps.at(module)(c.first).has_const()) + if (sigmap(c.first).has_const()) log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n", log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second)); @@ -258,8 +256,6 @@ struct FlattenWorker bool did_something = false; LogMakeDebugHdl mkdebug; - SigMap sigmap(module); - for (auto cell : module->selected_cells()) { if (!design->has(cell->type)) From 6268bdfe6f3f654d7fbde8ee879c190ec5b646a5 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 3 Jun 2020 17:41:45 +0000 Subject: [PATCH 11/13] flatten: simplify. `flatten` cannot derive modules in most cases because that would just yield processes, and it does not support `-autoproc`; in practice `flatten` has to be preceded by a call to `hierarchy`, which makes deriving unnecessary. --- passes/techmap/flatten.cc | 50 ++++++--------------------------------- 1 file changed, 7 insertions(+), 43 deletions(-) diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index 75345fcc1..c4054141d 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -51,15 +51,13 @@ void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) struct FlattenWorker { - dict>, RTLIL::Module*> cache; - pool flatten_do_list; pool flatten_done_list; pool flatten_keep_list; bool ignore_wb = false; - void flatten_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl) + void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl) { if (tpl->processes.size() != 0) { log("Flattening yielded processes:"); @@ -252,64 +250,30 @@ struct FlattenWorker if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb)) return false; - bool log_continue = false; bool did_something = false; - LogMakeDebugHdl mkdebug; for (auto cell : module->selected_cells()) { if (!design->has(cell->type)) continue; - if (cell->get_bool_attribute(ID::keep_hierarchy) || design->module(cell->type)->get_bool_attribute(ID::keep_hierarchy)) { + RTLIL::Module *tpl = design->module(cell->type); + if (tpl->get_blackbox_attribute(ignore_wb)) + continue; + + if (cell->get_bool_attribute(ID::keep_hierarchy) || tpl->get_bool_attribute(ID::keep_hierarchy)) { if (!flatten_keep_list[cell]) { log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell)); flatten_keep_list.insert(cell); } - if (!flatten_done_list[cell->type]) - flatten_do_list.insert(cell->type); continue; } - RTLIL::Module *tpl = design->module(cell->type); - dict parameters(cell->parameters); - - if (tpl->get_blackbox_attribute(ignore_wb)) - continue; - - std::pair> key(cell->type, parameters); - IdString derived_name; - auto it = cache.find(key); - if (it != cache.end()) { - derived_name = cell->type; - tpl = it->second; - } else { - if (parameters.size() != 0) { - mkdebug.on(); - derived_name = tpl->derive(design, parameters); - tpl = design->module(derived_name); - log_continue = true; - } - cache.emplace(std::move(key), tpl); - } - - if (log_continue) { - log_header(design, "Continuing FLATTEN pass.\n"); - log_continue = false; - mkdebug.off(); - } - log_debug("Flattening %s.%s (%s) using %s.\n", log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); - flatten_module(design, module, cell, tpl); + flatten_cell(design, module, cell, tpl); did_something = true; } - if (log_continue) { - log_header(design, "Continuing FLATTEN pass.\n"); - log_continue = false; - mkdebug.off(); - } - return did_something; } }; From d731fe054b8724997f5cf469018c03657d6e4f8a Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 3 Jun 2020 20:04:51 +0000 Subject: [PATCH 12/13] flatten: topologically sort modules. --- passes/techmap/flatten.cc | 106 ++++++++++++++++++-------------------- 1 file changed, 49 insertions(+), 57 deletions(-) diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index c4054141d..0a941d847 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -51,13 +51,9 @@ void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) struct FlattenWorker { - pool flatten_do_list; - pool flatten_done_list; - pool flatten_keep_list; - bool ignore_wb = false; - void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl) + void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, std::vector &new_cells) { if (tpl->processes.size() != 0) { log("Flattening yielded processes:"); @@ -197,6 +193,7 @@ struct FlattenWorker apply_prefix(cell->name, c_name); RTLIL::Cell *c = module->addCell(c_name, tpl_cell); + new_cells.push_back(c); design->select(module, c); for (auto &conn : c->connections()) @@ -245,15 +242,17 @@ struct FlattenWorker } } - bool flatten_module(RTLIL::Design *design, RTLIL::Module *module) + void flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool &used_modules) { if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb)) - return false; + return; - bool did_something = false; - - for (auto cell : module->selected_cells()) + std::vector worklist = module->selected_cells(); + while (!worklist.empty()) { + RTLIL::Cell *cell = worklist.back(); + worklist.pop_back(); + if (!design->has(cell->type)) continue; @@ -262,19 +261,17 @@ struct FlattenWorker continue; if (cell->get_bool_attribute(ID::keep_hierarchy) || tpl->get_bool_attribute(ID::keep_hierarchy)) { - if (!flatten_keep_list[cell]) { - log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell)); - flatten_keep_list.insert(cell); - } + log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell)); + used_modules.insert(tpl); continue; } - log_debug("Flattening %s.%s (%s) using %s.\n", log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); - flatten_cell(design, module, cell, tpl); - did_something = true; + log_debug("Flattening %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); + // If a design is fully selected and has a top module defined, topological sorting ensures that all cells + // added during flattening are black boxes, and flattening is finished in one pass. However, when flattening + // individual modules, this isn't the case, and the newly added cells might have to be flattened further. + flatten_cell(design, module, cell, tpl, worklist); } - - return did_something; } }; @@ -314,50 +311,45 @@ struct FlattenPass : public Pass { } extra_args(args, argidx, design); - RTLIL::Module *top_mod = nullptr; + RTLIL::Module *top = nullptr; if (design->full_selection()) - for (auto mod : design->modules()) - if (mod->get_bool_attribute(ID::top)) - top_mod = mod; + for (auto module : design->modules()) + if (module->get_bool_attribute(ID::top)) + top = module; - if (top_mod != nullptr) { - worker.flatten_do_list.insert(top_mod->name); - while (!worker.flatten_do_list.empty()) { - auto mod = design->module(*worker.flatten_do_list.begin()); - while (worker.flatten_module(design, mod)) { } - worker.flatten_done_list.insert(mod->name); - worker.flatten_do_list.erase(mod->name); - } - } else { - for (auto mod : design->modules().to_vector()) - while (worker.flatten_module(design, mod)) { } - } + pool used_modules; + if (top == nullptr) + used_modules = design->modules(); + else + used_modules.insert(top); - log_suppressed(); - log("No more expansions possible.\n"); - - if (top_mod != nullptr) - { - pool used_modules, new_used_modules; - new_used_modules.insert(top_mod->name); - while (!new_used_modules.empty()) { - pool queue; - queue.swap(new_used_modules); - for (auto modname : queue) - used_modules.insert(modname); - for (auto modname : queue) - for (auto cell : design->module(modname)->cells()) - if (design->module(cell->type) && !used_modules[cell->type]) - new_used_modules.insert(cell->type); - } - - for (auto mod : design->modules().to_vector()) - if (!used_modules[mod->name] && !mod->get_blackbox_attribute(worker.ignore_wb)) { - log("Deleting now unused module %s.\n", log_id(mod)); - design->remove(mod); + TopoSort> topo_modules; + pool worklist = used_modules; + while (!worklist.empty()) { + RTLIL::Module *module = worklist.pop(); + for (auto cell : module->selected_cells()) { + RTLIL::Module *tpl = design->module(cell->type); + if (tpl != nullptr) { + if (topo_modules.database.count(tpl) == 0) + worklist.insert(tpl); + topo_modules.edge(tpl, module); } + } } + if (!topo_modules.sort()) + log_error("Cannot flatten a design containing recursive instantiations.\n"); + + for (auto module : topo_modules.sorted) + worker.flatten_module(design, module, used_modules); + + if (top != nullptr) + for (auto module : design->modules().to_vector()) + if (!used_modules[module] && !module->get_blackbox_attribute(worker.ignore_wb)) { + log("Deleting now unused module %s.\n", log_id(module)); + design->remove(module); + } + log_pop(); } } FlattenPass; From 5a5a9b4ffe8b38eca7dc4fdfc56a16d401022fa2 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 3 Jun 2020 20:06:04 +0000 Subject: [PATCH 13/13] flatten: clean up log messages. --- passes/techmap/flatten.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index 0a941d847..027bb137d 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -261,7 +261,7 @@ struct FlattenWorker continue; if (cell->get_bool_attribute(ID::keep_hierarchy) || tpl->get_bool_attribute(ID::keep_hierarchy)) { - log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell)); + log("Keeping %s.%s (found keep_hierarchy attribute).\n", log_id(module), log_id(cell)); used_modules.insert(tpl); continue; }