mirror of https://github.com/YosysHQ/yosys.git
Call abc9 with "&write -n", and parse_xaiger() to cope
This commit is contained in:
Eddie Hung
parent
c767525441
commit
ab667d3d47
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@ -376,105 +376,98 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
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if (n0)
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module->connect(n0, State::S0);
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int c = f.get();
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if (c != 'c')
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log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
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c = f.get();
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log_assert(c == '\n');
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// Parse footer (symbol table, comments, etc.)
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std::string s;
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bool comment_seen = false;
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for (int c = f.peek(); c != EOF; c = f.peek()) {
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if (comment_seen || c == 'c') {
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if (!comment_seen) {
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f.ignore(1);
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c = f.peek();
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comment_seen = true;
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}
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if (c == '\n')
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break;
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f.ignore(1);
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// XAIGER extensions
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if (c == 'm') {
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uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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uint32_t lutNum = parse_xaiger_literal(f);
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uint32_t lutSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
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ConstEvalAig ce(module);
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for (unsigned i = 0; i < lutNum; ++i) {
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uint32_t rootNodeID = parse_xaiger_literal(f);
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uint32_t cutLeavesM = parse_xaiger_literal(f);
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log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
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RTLIL::Wire *output_sig = module->wire(stringf("\\__%d__", rootNodeID));
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uint32_t nodeID;
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RTLIL::SigSpec input_sig;
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for (unsigned j = 0; j < cutLeavesM; ++j) {
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nodeID = parse_xaiger_literal(f);
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log_debug2("\t%u\n", nodeID);
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RTLIL::Wire *wire = module->wire(stringf("\\__%d__", nodeID));
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log_assert(wire);
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input_sig.append(wire);
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}
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// TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size())
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ce.clear();
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ce.compute_deps(output_sig, input_sig.to_sigbit_pool());
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RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size());
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for (int j = 0; j < (1 << cutLeavesM); ++j) {
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int gray = j ^ (j >> 1);
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ce.set_incremental(input_sig, RTLIL::Const{gray, static_cast<int>(cutLeavesM)});
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RTLIL::SigBit o(output_sig);
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bool success YS_ATTRIBUTE(unused) = ce.eval(o);
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log_assert(success);
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log_assert(o.wire == nullptr);
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lut_mask[gray] = o.data;
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}
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RTLIL::Cell *output_cell = module->cell(stringf("\\__%d__$and", rootNodeID));
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log_assert(output_cell);
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module->remove(output_cell);
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module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
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for (int c = f.get(); c != EOF; c = f.get()) {
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// XAIGER extensions
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if (c == 'm') {
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uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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uint32_t lutNum = parse_xaiger_literal(f);
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uint32_t lutSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
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ConstEvalAig ce(module);
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for (unsigned i = 0; i < lutNum; ++i) {
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uint32_t rootNodeID = parse_xaiger_literal(f);
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uint32_t cutLeavesM = parse_xaiger_literal(f);
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log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
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RTLIL::Wire *output_sig = module->wire(stringf("\\__%d__", rootNodeID));
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uint32_t nodeID;
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RTLIL::SigSpec input_sig;
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for (unsigned j = 0; j < cutLeavesM; ++j) {
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nodeID = parse_xaiger_literal(f);
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log_debug2("\t%u\n", nodeID);
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RTLIL::Wire *wire = module->wire(stringf("\\__%d__", nodeID));
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log_assert(wire);
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input_sig.append(wire);
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}
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}
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else if (c == 'r') {
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uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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flopNum = parse_xaiger_literal(f);
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log_debug("flopNum = %u\n", flopNum);
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log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
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f.ignore(flopNum * sizeof(uint32_t));
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}
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else if (c == 'n') {
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parse_xaiger_literal(f);
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f >> s;
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log_debug("n: '%s'\n", s.c_str());
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}
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else if (c == 'h') {
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f.ignore(sizeof(uint32_t));
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uint32_t version YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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log_assert(version == 1);
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uint32_t ciNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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log_debug("ciNum = %u\n", ciNum);
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uint32_t coNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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log_debug("coNum = %u\n", coNum);
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piNum = parse_xaiger_literal(f);
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log_debug("piNum = %u\n", piNum);
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uint32_t poNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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log_debug("poNum = %u\n", poNum);
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uint32_t boxNum = parse_xaiger_literal(f);
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log_debug("boxNum = %u\n", boxNum);
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for (unsigned i = 0; i < boxNum; i++) {
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f.ignore(2*sizeof(uint32_t));
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uint32_t boxUniqueId = parse_xaiger_literal(f);
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log_assert(boxUniqueId > 0);
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uint32_t oldBoxNum = parse_xaiger_literal(f);
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RTLIL::Cell* cell = module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId));
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boxes.emplace_back(cell);
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// TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size())
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ce.clear();
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ce.compute_deps(output_sig, input_sig.to_sigbit_pool());
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RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size());
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for (int j = 0; j < (1 << cutLeavesM); ++j) {
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int gray = j ^ (j >> 1);
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ce.set_incremental(input_sig, RTLIL::Const{gray, static_cast<int>(cutLeavesM)});
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RTLIL::SigBit o(output_sig);
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bool success YS_ATTRIBUTE(unused) = ce.eval(o);
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log_assert(success);
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log_assert(o.wire == nullptr);
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lut_mask[gray] = o.data;
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}
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}
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else if (c == 'a' || c == 'i' || c == 'o' || c == 's') {
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uint32_t dataSize = parse_xaiger_literal(f);
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f.ignore(dataSize);
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log_debug("ignoring '%c'\n", c);
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}
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else {
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break;
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RTLIL::Cell *output_cell = module->cell(stringf("\\__%d__$and", rootNodeID));
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log_assert(output_cell);
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module->remove(output_cell);
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module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
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}
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}
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else
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log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
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else if (c == 'r') {
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uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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flopNum = parse_xaiger_literal(f);
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log_debug("flopNum = %u\n", flopNum);
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log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
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f.ignore(flopNum * sizeof(uint32_t));
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}
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else if (c == 'n') {
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parse_xaiger_literal(f);
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f >> s;
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log_debug("n: '%s'\n", s.c_str());
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}
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else if (c == 'h') {
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f.ignore(sizeof(uint32_t));
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uint32_t version YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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log_assert(version == 1);
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uint32_t ciNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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log_debug("ciNum = %u\n", ciNum);
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uint32_t coNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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log_debug("coNum = %u\n", coNum);
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piNum = parse_xaiger_literal(f);
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log_debug("piNum = %u\n", piNum);
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uint32_t poNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
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log_debug("poNum = %u\n", poNum);
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uint32_t boxNum = parse_xaiger_literal(f);
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log_debug("boxNum = %u\n", boxNum);
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for (unsigned i = 0; i < boxNum; i++) {
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f.ignore(2*sizeof(uint32_t));
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uint32_t boxUniqueId = parse_xaiger_literal(f);
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log_assert(boxUniqueId > 0);
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uint32_t oldBoxNum = parse_xaiger_literal(f);
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RTLIL::Cell* cell = module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId));
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boxes.emplace_back(cell);
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}
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}
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else if (c == 'a' || c == 'i' || c == 'o' || c == 's') {
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uint32_t dataSize = parse_xaiger_literal(f);
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f.ignore(dataSize);
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log_debug("ignoring '%c'\n", c);
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}
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else {
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break;
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}
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}
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post_process();
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@ -30,7 +30,7 @@
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"&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\
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"&mfs; &ps -l"
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#else
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#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l"
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#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l; &verify -s"
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#endif
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@ -311,7 +311,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
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for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
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abc9_script = abc9_script.erase(pos, strlen("&mfs"));
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abc9_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
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abc9_script += stringf("; &write -n %s/output.aig", tempdir_name.c_str());
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abc9_script = add_echos_to_abc9_cmd(abc9_script);
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for (size_t i = 0; i+1 < abc9_script.size(); i++)
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