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abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_

This commit is contained in:
Eddie Hung 2020-05-29 17:17:40 -07:00
parent 9c6d216a06
commit d3b53bc495
3 changed files with 25 additions and 7 deletions
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27
passes/techmap/abc9_ops.cc
View File

@ -232,10 +232,8 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
auto w = unmap_module->addWire(port, derived_module->wire(port));
// Do not propagate (* init *) values into the box,
// in fact, remove it from outside too
if (w->port_output && w->attributes.erase(ID::init)) {
auto r = unmap_module->addWire(stringf("\\_TECHMAP_REMOVEINIT_%s_", log_id(port)));
unmap_module->connect(r, State::S1);
}
if (w->port_output)
w->attributes.erase(ID::init);
}
unmap_module->ports = derived_module->ports;
unmap_module->check();
@ -1147,6 +1145,20 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
}
}
SigMap initmap;
if (dff_mode) {
// Build a sigmap prioritising bits with (* init *)
initmap.set(module);
for (auto w : module->wires()) {
auto it = w->attributes.find(ID::init);
if (it == w->attributes.end())
continue;
for (auto i = 0; i < GetSize(w); i++)
if (it->second[i] == State::S0 || it->second[i] == State::S1)
initmap.add(w);
}
}
std::vector<Cell*> boxes;
for (auto cell : module->cells().to_vector()) {
if (cell->has_keep_attr())
@ -1156,8 +1168,13 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// $_DFF_[NP]_ cells since flop box already has all the information
// we need to reconstruct them
if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep)) {
module->connect(cell->getPort(ID::Q), cell->getPort(ID::D));
SigBit Q = cell->getPort(ID::Q);
module->connect(Q, cell->getPort(ID::D));
module->remove(cell);
auto Qi = initmap(Q);
auto it = Qi.wire->attributes.find(ID::init);
if (it != Qi.wire->attributes.end())
it->second[Qi.offset] = State::Sx;
}
else if (cell->type.in(ID($_AND_), ID($_NOT_)))
module->remove(cell);

2
techlibs/common/abc9_unmap.v
View File

@ -1,5 +1,5 @@
(* techmap_celltype = "$__DFF_N__$abc9_flop $__DFF_P__$abc9_flop" *)
module $__DFF_x__$abc9_flop (input C, D, Q, output n1);
module $__DFF_x__$abc9_flop (input C, D, (* init = 1'b0 *) input Q, output n1);
parameter _TECHMAP_CELLTYPE_ = "";
generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N__$abc9_flop")
$_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));

3
tests/various/abc9.ys
View File

@ -97,4 +97,5 @@ select -assert-count 3 t:$_DFF_N_
select -assert-none c:ff1 c:ff2 c:ff4 %% c:* %D
clean
select -assert-count 2 a:init
select -assert-none w:w w:z %% a:init %D
select -assert-count 1 w:w a:init %i
select -assert-count 1 c:ff4 %co c:ff4 %d %a a:init %i