mirror of https://github.com/YosysHQ/yosys.git
Bugfix in fsm_detect
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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e0ba78bdf2
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@ -158,22 +158,24 @@ static void detect_fsm(RTLIL::Wire *wire)
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std::set<sig2driver_entry_t> cellport_list;
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sig2user.find(sig_q, cellport_list);
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auto sig_q_bits = sig_q.to_sigbit_pool();
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for (auto &cellport : cellport_list)
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{
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RTLIL::Cell *cell = cellport.first;
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bool set_output = false, clr_output = false;
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if (cell->type == "$ne")
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if (cell->type.in("$ne", "$reduce_or", "$reduce_bool"))
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set_output = true;
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if (cell->type == "$eq")
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if (cell->type.in("$eq", "$logic_not", "$reduce_and"))
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clr_output = true;
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if (!set_output && !clr_output) {
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clr_output = true;
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if (set_output || clr_output) {
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for (auto &port_it : cell->connections())
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if (port_it.first != "\\A" || port_it.first != "\\Y")
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clr_output = false;
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for (auto bit : assign_map(port_it.second))
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if (bit.wire != nullptr && !sig_q_bits.count(bit))
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goto next_cellport;
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}
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if (set_output || clr_output) {
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@ -184,6 +186,7 @@ static void detect_fsm(RTLIL::Wire *wire)
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ce.set(sig, val);
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}
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}
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next_cellport:;
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}
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SigSpec sig_y = sig_d, sig_undef;
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