mirror of https://github.com/YosysHQ/yosys.git
Add abc9_ops -check, -prep_times, -write_box for required times
This commit is contained in:
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5e280a3b59
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b2259a9201
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@ -131,6 +131,7 @@ struct Abc9Pass : public ScriptPass
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std::stringstream exe_cmd;
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bool dff_mode, cleanup;
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std::string box_file;
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void clear_flags() YS_OVERRIDE
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{
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@ -138,6 +139,7 @@ struct Abc9Pass : public ScriptPass
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exe_cmd << "abc9_exe";
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dff_mode = false;
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cleanup = true;
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box_file.clear();
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -154,7 +156,7 @@ struct Abc9Pass : public ScriptPass
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std::string arg = args[argidx];
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if ((arg == "-exe" || arg == "-script" || arg == "-D" ||
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/* arg == "-S" || */ arg == "-lut" || arg == "-luts" ||
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arg == "-box" || arg == "-W") &&
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/*arg == "-box" ||*/ arg == "-W") &&
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argidx+1 < args.size()) {
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exe_cmd << " " << arg << " " << args[++argidx];
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continue;
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@ -173,6 +175,10 @@ struct Abc9Pass : public ScriptPass
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cleanup = false;
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continue;
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}
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if (arg == "-box" && argidx+1 < args.size()) {
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box_file = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -185,11 +191,12 @@ struct Abc9Pass : public ScriptPass
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void script() YS_OVERRIDE
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{
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if (check_label("pre")) {
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run("abc9_ops -check");
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run("scc -set_attr abc9_scc_id {}");
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if (help_mode)
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run("abc9_ops -break_scc -prep_holes [-dff]", "(option for -dff)");
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run("abc9_ops -break_scc -prep_times -prep_holes [-dff]", "(option for -dff)");
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else
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run("abc9_ops -break_scc -prep_holes" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
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run("abc9_ops -break_scc -prep_times -prep_holes" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
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run("select -set abc9_holes A:abc9_holes");
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run("flatten -wb @abc9_holes");
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run("techmap @abc9_holes");
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@ -203,8 +210,9 @@ struct Abc9Pass : public ScriptPass
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if (check_label("map")) {
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if (help_mode) {
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run("foreach module in selection");
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run(" abc9_ops -write_box [(-box value)|(null)] <abc-temp-dir>/input.box");
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run(" write_xaiger -map <abc-temp-dir>/input.sym <abc-temp-dir>/input.xaig");
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run(" abc9_exe [options] -cwd <abc-temp-dir>");
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run(" abc9_exe [options] -cwd <abc-temp-dir> -box <abc-temp-dir>/input.box");
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run(" read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig");
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run(" abc9_ops -reintegrate");
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}
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@ -229,6 +237,10 @@ struct Abc9Pass : public ScriptPass
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tempdir_name[0] = tempdir_name[4] = '_';
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tempdir_name = make_temp_dir(tempdir_name);
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if (box_file.empty())
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run(stringf("abc9_ops -write_box (null) %s/input.box", tempdir_name.c_str()));
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else
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run(stringf("abc9_ops -write_box %s %s/input.box", box_file.c_str(), tempdir_name.c_str()));
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run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
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int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs");
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@ -238,10 +250,8 @@ struct Abc9Pass : public ScriptPass
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active_design->scratchpad_get_int("write_xaiger.num_inputs"),
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num_outputs);
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if (num_outputs) {
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run(stringf("%s -cwd %s", exe_cmd.str().c_str(), tempdir_name.c_str()),
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"abc9_exe [options] -cwd <abc-temp-dir>");
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run(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod->name), tempdir_name.c_str(), tempdir_name.c_str()),
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"read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig");
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run(stringf("%s -cwd %s -box %s/input.box", exe_cmd.str().c_str(), tempdir_name.c_str(), tempdir_name.c_str()));
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run(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod->name), tempdir_name.c_str(), tempdir_name.c_str()));
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run("abc9_ops -reintegrate");
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}
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else
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@ -23,6 +23,8 @@
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#include "kernel/utils.h"
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#include "kernel/celltypes.h"
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#define ABC9_DELAY_BASE_ID 9000
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -33,6 +35,48 @@ inline std::string remap_name(RTLIL::IdString abc9_name)
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return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
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}
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void check(RTLIL::Design *design)
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{
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dict<IdString,IdString> box_lookup;
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for (auto m : design->modules()) {
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auto it = m->attributes.find(ID(abc9_box_id));
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if (it == m->attributes.end())
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continue;
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if (m->name.begins_with("$paramod"))
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continue;
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auto id = it->second.as_int();
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auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
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if (!r.second)
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log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
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log_id(m), id, log_id(r.first->second));
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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for (const auto &port_name : m->ports) {
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auto w = m->wire(port_name);
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log_assert(w);
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input) {
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if (carry_in != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
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carry_in = port_name;
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}
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if (w->port_output) {
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if (carry_out != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(m));
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carry_out = port_name;
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}
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}
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}
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if (carry_in != IdString() && carry_out == IdString())
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log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
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}
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}
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void break_scc(RTLIL::Module *module)
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{
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// For every unique SCC found, (arbitrarily) find the first
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@ -301,6 +345,7 @@ void prep_holes(RTLIL::Module *module, bool dff)
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}
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cell->attributes["\\abc9_box_seq"] = box_list.size();
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//log_debug("%s.%s is box %d\n", log_id(module), log_id(cell), box_list.size());
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box_list.emplace_back(cell);
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}
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log_assert(!box_list.empty());
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@ -318,8 +363,8 @@ void prep_holes(RTLIL::Module *module, bool dff)
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log_assert(orig_box_module);
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IdString derived_name = orig_box_module->derive(design, cell->parameters);
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RTLIL::Module* box_module = design->module(derived_name);
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if (box_module->has_processes())
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Pass::call_on_module(design, box_module, "proc");
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cell->type = derived_name;
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cell->parameters.clear();
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int box_inputs = 0;
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auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
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@ -328,6 +373,9 @@ void prep_holes(RTLIL::Module *module, bool dff)
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holes_cell = holes_module->addCell(cell->name, cell->type);
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holes_cell->parameters = cell->parameters;
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r.first->second = holes_cell;
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if (box_module->has_processes())
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Pass::call_on_module(design, box_module, "proc");
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}
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auto r2 = box_ports.insert(cell->type);
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@ -339,25 +387,15 @@ void prep_holes(RTLIL::Module *module, bool dff)
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auto w = box_module->wire(port_name);
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log_assert(w);
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input) {
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if (carry_in != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
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if (w->port_input)
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carry_in = port_name;
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}
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if (w->port_output) {
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if (carry_out != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
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if (w->port_output)
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carry_out = port_name;
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}
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}
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else
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r2.first->second.push_back(port_name);
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}
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if (carry_in != IdString() && carry_out == IdString())
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log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
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if (carry_in != IdString()) {
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r2.first->second.push_back(carry_in);
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r2.first->second.push_back(carry_out);
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@ -423,6 +461,116 @@ void prep_holes(RTLIL::Module *module, bool dff)
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}
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}
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void prep_times(RTLIL::Design *design)
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{
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std::set<int> delays;
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std::vector<Cell*> boxes;
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std::map<int,std::vector<int>> requireds;
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for (auto module : design->selected_modules()) {
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if (module->get_bool_attribute("\\abc9_holes"))
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continue;
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if (module->processes.size() > 0) {
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log("Skipping module %s as it contains processes.\n", log_id(module));
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continue;
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}
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boxes.clear();
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for (auto cell : module->cells()) {
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if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_), ID($__ABC9_DELAY)))
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continue;
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RTLIL::Module* inst_module = module->design->module(cell->type);
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if (!inst_module)
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continue;
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if (!inst_module->get_blackbox_attribute())
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continue;
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// Flop inputs cannot have required times
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// (required time should be captured by flop box)
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// TODO: enforce this
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if (cell->attributes.count(ID(abc9_box_id)))
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continue;
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boxes.emplace_back(cell);
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}
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delays.clear();
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requireds.clear();
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for (auto cell : boxes) {
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RTLIL::Module* inst_module = module->design->module(cell->type);
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for (auto &conn : cell->connections_) {
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auto port_wire = inst_module->wire(conn.first);
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if (!port_wire->port_input)
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continue;
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auto it = port_wire->attributes.find("\\abc9_required");
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if (it == port_wire->attributes.end())
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continue;
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int count = 0;
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requireds.clear();
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if (it->second.flags == 0) {
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count = 1;
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requireds[it->second.as_int()].push_back(0);
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}
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else
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for (const auto &tok : split_tokens(it->second.decode_string()))
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requireds[atoi(tok.c_str())].push_back(count++);
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if (count > 1 && count != GetSize(port_wire))
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log_error("%s.%s is %d bits wide but abc9_required = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
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GetSize(port_wire), log_signal(it->second), count);
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SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
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for (const auto &i : requireds) {
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delays.insert(i.first);
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for (auto offset : i.second) {
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auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
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box->setPort(ID(I), conn.second[offset]);
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box->setPort(ID(O), O[offset]);
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box->setParam(ID(DELAY), i.first);
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conn.second[offset] = O[offset];
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}
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}
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}
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}
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std::stringstream ss;
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bool first = true;
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for (auto d : delays)
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if (first) {
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first = false;
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ss << d;
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}
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else
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ss << " " << d;
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module->attributes[ID(abc9_delays)] = ss.str();
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}
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}
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void write_box(RTLIL::Module *module, const std::string &src, const std::string &dst) {
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std::ofstream ofs(dst);
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log_assert(ofs.is_open());
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// Since ABC can only accept one box file, we have to copy
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// over the existing box file
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if (src != "(null)") {
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std::ifstream ifs(src);
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ofs << ifs.rdbuf() << std::endl;
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ifs.close();
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}
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auto it = module->attributes.find(ID(abc9_delays));
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if (it != module->attributes.end()) {
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for (const auto &tok : split_tokens(it->second.decode_string())) {
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int d = atoi(tok.c_str());
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ofs << "$__ABC9_DELAY@" << d << " " << ABC9_DELAY_BASE_ID + d << " 0 1 1" << std::endl;
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ofs << d << std::endl;
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}
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}
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ofs.close();
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}
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void reintegrate(RTLIL::Module *module)
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{
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auto design = module->design;
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@ -438,8 +586,6 @@ void reintegrate(RTLIL::Module *module)
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module->addWire(remap_name(w->name), GetSize(w));
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dict<IdString,IdString> box_lookup;
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dict<IdString,std::vector<IdString>> box_ports;
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for (auto m : design->modules()) {
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auto it = m->attributes.find(ID(abc9_box_id));
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if (it == m->attributes.end())
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@ -447,51 +593,19 @@ void reintegrate(RTLIL::Module *module)
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if (m->name.begins_with("$paramod"))
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continue;
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auto id = it->second.as_int();
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auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
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if (!r.second)
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log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
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log_id(m), id, log_id(r.first->second));
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auto r YS_ATTRIBUTE(unused) = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
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log_assert(r.second);
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auto r2 = box_ports.insert(m->name);
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if (r2.second) {
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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for (const auto &port_name : m->ports) {
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auto w = m->wire(port_name);
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log_assert(w);
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input) {
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if (carry_in != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
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carry_in = port_name;
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}
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if (w->port_output) {
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if (carry_out != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(m));
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carry_out = port_name;
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}
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}
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else
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r2.first->second.push_back(port_name);
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}
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if (carry_in != IdString() && carry_out == IdString())
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log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
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if (carry_in != IdString()) {
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r2.first->second.push_back(carry_in);
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r2.first->second.push_back(carry_out);
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}
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}
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}
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pool<IdString> delay_boxes;
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std::vector<Cell*> boxes;
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for (auto cell : module->cells().to_vector()) {
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if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_)))
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module->remove(cell);
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else if (cell->type.begins_with("$paramod$__ABC9_DELAY\\DELAY=")) {
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delay_boxes.insert(cell->name);
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module->remove(cell);
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}
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else if (cell->attributes.erase("\\abc9_box_seq"))
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boxes.emplace_back(cell);
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}
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@ -501,6 +615,7 @@ void reintegrate(RTLIL::Module *module)
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dict<RTLIL::Cell*,RTLIL::Cell*> not2drivers;
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dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
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dict<IdString,std::vector<IdString>> box_ports;
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std::map<IdString, int> cell_stats;
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for (auto mapped_cell : mapped_mod->cells())
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{
|
||||
|
@ -551,16 +666,6 @@ void reintegrate(RTLIL::Module *module)
|
|||
}
|
||||
|
||||
if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) {
|
||||
// Convert buffer into direct connection
|
||||
if (mapped_cell->type == ID($lut) &&
|
||||
GetSize(mapped_cell->getPort(ID::A)) == 1 &&
|
||||
mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
|
||||
SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name));
|
||||
SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name));
|
||||
module->connect(my_y, my_a);
|
||||
log_abort();
|
||||
continue;
|
||||
}
|
||||
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
|
||||
cell->parameters = mapped_cell->parameters;
|
||||
cell->attributes = mapped_cell->attributes;
|
||||
|
@ -588,6 +693,16 @@ void reintegrate(RTLIL::Module *module)
|
|||
bit_drivers[i].insert(mapped_cell->name);
|
||||
}
|
||||
}
|
||||
else if (delay_boxes.count(mapped_cell->name)) {
|
||||
SigBit I = mapped_cell->getPort(ID(i));
|
||||
SigBit O = mapped_cell->getPort(ID(o));
|
||||
if (I.wire)
|
||||
I.wire = module->wires_.at(remap_name(I.wire->name));
|
||||
log_assert(O.wire);
|
||||
O.wire = module->wires_.at(remap_name(O.wire->name));
|
||||
module->connect(O, I);
|
||||
continue;
|
||||
}
|
||||
else {
|
||||
RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
|
||||
log_assert(existing_cell);
|
||||
|
@ -621,6 +736,30 @@ void reintegrate(RTLIL::Module *module)
|
|||
bit_drivers[i].insert(mapped_cell->name);
|
||||
}
|
||||
|
||||
auto r2 = box_ports.insert(cell->type);
|
||||
if (r2.second) {
|
||||
// Make carry in the last PI, and carry out the last PO
|
||||
// since ABC requires it this way
|
||||
IdString carry_in, carry_out;
|
||||
for (const auto &port_name : box_module->ports) {
|
||||
auto w = box_module->wire(port_name);
|
||||
log_assert(w);
|
||||
if (w->get_bool_attribute("\\abc9_carry")) {
|
||||
if (w->port_input)
|
||||
carry_in = port_name;
|
||||
if (w->port_output)
|
||||
carry_out = port_name;
|
||||
}
|
||||
else
|
||||
r2.first->second.push_back(port_name);
|
||||
}
|
||||
|
||||
if (carry_in != IdString()) {
|
||||
r2.first->second.push_back(carry_in);
|
||||
r2.first->second.push_back(carry_out);
|
||||
}
|
||||
}
|
||||
|
||||
int input_count = 0, output_count = 0;
|
||||
for (const auto &port_name : box_ports.at(cell->type)) {
|
||||
RTLIL::Wire *w = box_module->wire(port_name);
|
||||
|
@ -807,16 +946,23 @@ struct Abc9OpsPass : public Pass {
|
|||
{
|
||||
log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
|
||||
|
||||
bool check_mode = false;
|
||||
bool prep_times_mode = false;
|
||||
bool break_scc_mode = false;
|
||||
bool unbreak_scc_mode = false;
|
||||
bool prep_dff_mode = false;
|
||||
bool prep_holes_mode = false;
|
||||
bool prep_dff_mode = false;
|
||||
std::string write_box_src, write_box_dst;
|
||||
bool reintegrate_mode = false;
|
||||
bool dff_mode = false;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
std::string arg = args[argidx];
|
||||
if (arg == "-check") {
|
||||
check_mode = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-break_scc") {
|
||||
break_scc_mode = true;
|
||||
continue;
|
||||
|
@ -833,6 +979,17 @@ struct Abc9OpsPass : public Pass {
|
|||
prep_holes_mode = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-prep_times") {
|
||||
prep_times_mode = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-write_box" && argidx+2 < args.size()) {
|
||||
write_box_src = args[++argidx];
|
||||
write_box_dst = args[++argidx];
|
||||
rewrite_filename(write_box_src);
|
||||
rewrite_filename(write_box_dst);
|
||||
continue;
|
||||
}
|
||||
if (arg == "-reintegrate") {
|
||||
reintegrate_mode = true;
|
||||
continue;
|
||||
|
@ -845,6 +1002,13 @@ struct Abc9OpsPass : public Pass {
|
|||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
// TODO: Check at least one mode given
|
||||
|
||||
if (check_mode)
|
||||
check(design);
|
||||
if (prep_times_mode)
|
||||
prep_times(design);
|
||||
|
||||
for (auto mod : design->selected_modules()) {
|
||||
if (mod->get_bool_attribute("\\abc9_holes"))
|
||||
continue;
|
||||
|
@ -858,10 +1022,12 @@ struct Abc9OpsPass : public Pass {
|
|||
break_scc(mod);
|
||||
if (unbreak_scc_mode)
|
||||
unbreak_scc(mod);
|
||||
if (prep_dff_mode)
|
||||
prep_dff(mod);
|
||||
if (prep_holes_mode)
|
||||
prep_holes(mod, dff_mode);
|
||||
if (prep_dff_mode)
|
||||
prep_dff(mod);
|
||||
if (!write_box_src.empty())
|
||||
write_box(mod, write_box_src, write_box_dst);
|
||||
if (reintegrate_mode)
|
||||
reintegrate(mod);
|
||||
}
|
||||
|
|
|
@ -33,6 +33,11 @@ endmodule
|
|||
module \$__ABC9_FF_ (input D, output Q);
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id = (9000+DELAY) *)
|
||||
module \$__ABC9_DELAY (input I, output O);
|
||||
parameter DELAY = 0;
|
||||
endmodule
|
||||
|
||||
// Box to emulate async behaviour of FDC*
|
||||
(* abc9_box_id = 1000, lib_whitebox *)
|
||||
module \$__ABC9_ASYNC0 (input A, S, output Y);
|
||||
|
|
Loading…
Reference in New Issue