mirror of https://github.com/YosysHQ/yosys.git
opt_expr: Add more $alu optimizations.
Detect the places in the $alu where the carry bit is constant (due to const A[i] == B[i] ^ BI) and split it into smaller $alu at these points. Also, make the existing const-carry detection for low bits more generic (now handles cases where both BI and CI are constant, but not equal to one another). Fixes #1912.
This commit is contained in:
Marcelina Kościelnicka
parent
7a36728b2f
commit
6c16fd760b
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@ -717,31 +717,27 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
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RTLIL::SigSpec sig_co = cell->getPort(ID::CO);
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bool sub = (sig_ci == State::S1 && sig_bi == State::S1);
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if (sig_bi != State::S0 && sig_bi != State::S1)
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goto skip_fine_alu;
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if (sig_ci != State::S0 && sig_ci != State::S1)
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goto skip_fine_alu;
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// If not a subtraction, yet there is a carry or B is inverted
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// then no optimisation is possible as carry will not be constant
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if (!sub && (sig_ci != State::S0 || sig_bi != State::S0))
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goto next_cell;
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bool bi = sig_bi == State::S1;
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bool ci = sig_ci == State::S1;
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int i;
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for (i = 0; i < GetSize(sig_y); i++) {
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RTLIL::SigBit b = sig_b.at(i, State::Sx);
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RTLIL::SigBit a = sig_a.at(i, State::Sx);
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if (b == State::S0 && a != State::Sx) {
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module->connect(sig_y[i], sig_a[i]);
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module->connect(sig_x[i], sub ? module->Not(NEW_ID, a).as_bit() : a);
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module->connect(sig_co[i], sub ? State::S1 : State::S0);
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if (b == ((bi ^ ci) ? State::S1 : State::S0) && a != State::Sx) {
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module->connect(sig_y[i], a);
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module->connect(sig_x[i], ci ? module->Not(NEW_ID, a).as_bit() : a);
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module->connect(sig_co[i], ci ? State::S1 : State::S0);
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}
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else if (sub && b == State::S1 && a == State::S1) {
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module->connect(sig_y[i], State::S0);
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module->connect(sig_x[i], module->Not(NEW_ID, a));
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module->connect(sig_co[i], State::S0);
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}
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else if (!sub && a == State::S0 && b != State::Sx) {
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module->connect(sig_y[i], b);
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module->connect(sig_x[i], b);
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module->connect(sig_co[i], State::S0);
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else if (a == (ci ? State::S1 : State::S0) && b != State::Sx) {
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module->connect(sig_y[i], bi ? module->Not(NEW_ID, b).as_bit() : b);
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module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID, b).as_bit() : b);
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module->connect(sig_co[i], ci ? State::S1 : State::S0);
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}
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else
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break;
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@ -758,6 +754,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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}
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}
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skip_fine_alu:
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if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($shift), ID($shiftx), ID($shl), ID($shr), ID($sshl), ID($sshr),
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ID($lt), ID($le), ID($ge), ID($gt), ID($neg), ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow)))
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@ -1089,7 +1086,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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// If not a subtraction, yet there is a carry or B is inverted
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// then no optimisation is possible as carry will not be constant
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if (!sub && (sig_ci != State::S0 || sig_bi != State::S0))
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goto next_cell;
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goto skip_identity;
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}
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if (!sub && a.is_fully_const() && a.as_bool() == false)
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@ -1163,6 +1160,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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goto next_cell;
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}
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}
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skip_identity:
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if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) &&
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cell->getPort(ID::A) == State::S0 && cell->getPort(ID::B) == State::S1) {
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@ -1530,6 +1528,99 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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}
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// Find places in $alu cell where the carry is constant, and split it at these points.
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if (do_fine && !keepdc && cell->type == ID($alu))
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{
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bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
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bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
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bool is_signed = a_signed && b_signed;
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RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
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RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
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RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
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RTLIL::SigSpec sig_bi = assign_map(cell->getPort(ID::BI));
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if (GetSize(sig_a) == 0)
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sig_a = State::S0;
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if (GetSize(sig_b) == 0)
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sig_b = State::S0;
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sig_a.extend_u0(GetSize(sig_y), is_signed);
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sig_b.extend_u0(GetSize(sig_y), is_signed);
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if (sig_bi != State::S0 && sig_bi != State::S1)
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goto skip_alu_split;
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std::vector<std::pair<int, State>> split_points;
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for (int i = 0; i < GetSize(sig_y); i++) {
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SigBit bit_a = sig_a[i];
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SigBit bit_b = sig_b[i];
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if (bit_a != State::S0 && bit_a != State::S1)
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continue;
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if (bit_b != State::S0 && bit_b != State::S1)
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continue;
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if (sig_bi == State::S1) {
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if (bit_b == State::S0)
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bit_b = State::S1;
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else
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bit_b = State::S0;
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}
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if (bit_a != bit_b)
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continue;
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split_points.push_back(std::make_pair(i + 1, bit_a.data));
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}
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if (split_points.empty() || split_points[0].first == GetSize(sig_y))
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goto skip_alu_split;
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for (auto &p : split_points)
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log_debug("Splitting $alu cell `%s' in module `%s' at const-carry point %d.\n",
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cell->name.c_str(), module->name.c_str(), p.first);
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if (split_points.back().first != GetSize(sig_y))
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split_points.push_back(std::make_pair(GetSize(sig_y), State::Sx));
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RTLIL::SigSpec sig_ci = assign_map(cell->getPort(ID::CI));
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int prev = 0;
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RTLIL::SigSpec sig_x = assign_map(cell->getPort(ID::X));
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RTLIL::SigSpec sig_co = assign_map(cell->getPort(ID::CO));
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for (auto &p : split_points) {
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int cur = p.first;
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int sz = cur - prev;
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bool last = cur == GetSize(sig_y);
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RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
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c->setPort(ID::A, sig_a.extract(prev, sz));
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c->setPort(ID::B, sig_b.extract(prev, sz));
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c->setPort(ID::BI, sig_bi);
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c->setPort(ID::CI, sig_ci);
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c->setPort(ID::Y, sig_y.extract(prev, sz));
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c->setPort(ID::X, sig_x.extract(prev, sz));
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RTLIL::SigSpec new_co = sig_co.extract(prev, sz);
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if (p.second != State::Sx) {
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module->connect(new_co[sz-1], p.second);
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RTLIL::Wire *dummy = module->addWire(NEW_ID);
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new_co[sz-1] = dummy;
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}
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c->setPort(ID::CO, new_co);
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c->parameters[ID::A_WIDTH] = sz;
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c->parameters[ID::B_WIDTH] = sz;
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c->parameters[ID::Y_WIDTH] = sz;
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c->parameters[ID::A_SIGNED] = last ? a_signed : false;
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c->parameters[ID::B_SIGNED] = last ? b_signed : false;
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prev = p.first;
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sig_ci = p.second;
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}
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cover("opt.opt_expr.alu_split");
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module->remove(cell);
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did_something = true;
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goto next_cell;
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}
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skip_alu_split:
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// remove redundant pairs of bits in ==, ===, !=, and !==
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// replace cell with const driver if inputs can't be equal
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if (do_fine && cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex)))
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@ -5,7 +5,7 @@ endmodule
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EOT
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alumacc
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equiv_opt opt_expr -fine
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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@ -30,7 +30,7 @@ assign y = {a,1'b1} - 1'b1;
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endmodule
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EOT
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equiv_opt opt_expr -fine
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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@ -43,7 +43,7 @@ assign y = {a,3'b101} - 1'b1;
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endmodule
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EOT
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equiv_opt opt_expr -fine
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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@ -57,7 +57,55 @@ endmodule
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EOT
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alumacc
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equiv_opt opt_expr -fine
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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design -reset
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read_verilog <<EOT
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module test(input [1:0] a, output [3:0] y);
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assign y = -{a[1], 2'b10, a[0]};
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt -fine
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design -load postopt
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select -assert-count 1 t:$alu
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select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
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select -assert-count 1 t:$not
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select -assert-count none t:$alu t:$not t:* %D %D
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design -reset
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read_verilog <<EOT
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module test(input [3:0] a, input [2:0] b, output [5:0] y);
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assign y = {a[3:2], 1'b1, a[1:0]} + {b[2], 2'b11, b[1:0]};
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt -fine
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design -load postopt
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dump
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select -assert-count 2 t:$alu
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select -assert-count 1 t:$alu r:Y_WIDTH=2 %i
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select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
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select -assert-count none t:$alu t:* %D
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design -reset
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read_verilog <<EOT
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module test(input [3:0] a, input [3:0] b, output [5:0] y);
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assign y = {a[3:2], 1'b0, a[1:0]} + {b[3:2], 1'b0, b[1:0]};
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt -fine
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design -load postopt
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select -assert-count 2 t:$alu
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select -assert-count 2 t:$alu r:Y_WIDTH=3 %i
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select -assert-count none t:$alu t:* %D
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