mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1661 from YosysHQ/eddie/abc9_required
abc9: add support for required times
This commit is contained in:
Eddie Hung
GitHub
commit
0671ae7d79
13
README.md
13
README.md
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@ -373,10 +373,15 @@ Verilog Attributes and non-standard features
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`abc9` to preserve the integrity of carry-chains. Specifying this attribute
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onto a bus port will affect only its most significant bit.
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- The port attribute ``abc9_arrival`` specifies an integer (for output ports
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only) to be used as the arrival time of this sequential port. It can be used,
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for example, to specify the clk-to-Q delay of a flip-flop for consideration
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during `abc9` techmapping.
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- The output port attribute ``abc9_arrival`` specifies an integer, or a string
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of space-separated integers to be used as the arrival time of this blackbox
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port. It can be used, for example, to specify the clk-to-Q delay of a flip-
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flop output for consideration during `abc9` techmapping.
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- The input port attribute ``abc9_required`` specifies an integer, or a string
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of space-separated integers to be used as the required time of this blackbox
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port. It can be used, for example, to specify the setup-time of a flip-flop
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input for consideration during `abc9` techmapping.
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- The module attribute ``abc9_flop`` is a boolean marking the module as a
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flip-flop. This allows `abc9` to analyse its contents in order to perform
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@ -184,7 +184,7 @@ struct XAigerWriter
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}
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}
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dict<IdString,dict<IdString,int>> arrival_cache;
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dict<IdString,dict<IdString,std::vector<int>>> arrivals_cache;
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for (auto cell : module->cells()) {
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RTLIL::Module* inst_module = module->design->module(cell->type);
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if (!cell->has_keep_attr()) {
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@ -236,29 +236,50 @@ struct XAigerWriter
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box_list.resize(abc9_box_seq+1);
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box_list[abc9_box_seq] = cell;
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// Only flop boxes may have arrival times
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// (all others are combinatorial)
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abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
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if (!abc9_flop)
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continue;
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}
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auto &cell_arrivals = arrival_cache[cell->type];
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auto &cell_arrivals = arrivals_cache[cell->type];
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for (const auto &conn : cell->connections()) {
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auto port_wire = inst_module->wire(conn.first);
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if (!port_wire->port_output)
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continue;
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auto r = cell_arrivals.insert(conn.first);
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auto &arrival = r.first->second;
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auto &arrivals = r.first->second;
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if (r.second) {
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auto port_wire = inst_module->wire(conn.first);
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if (port_wire->port_output) {
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auto it = port_wire->attributes.find("\\abc9_arrival");
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if (it != port_wire->attributes.end()) {
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if (it->second.flags != 0)
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log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
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arrival = it->second.as_int();
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}
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}
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auto it = port_wire->attributes.find("\\abc9_arrival");
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if (it == port_wire->attributes.end())
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continue;
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if (it->second.flags == 0)
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arrivals.emplace_back(it->second.as_int());
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else
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for (const auto &tok : split_tokens(it->second.decode_string()))
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arrivals.push_back(atoi(tok.c_str()));
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}
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if (arrivals.empty())
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continue;
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if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire))
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log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
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GetSize(port_wire), log_signal(it->second), GetSize(arrivals));
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auto jt = arrivals.begin();
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#ifndef NDEBUG
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if (ys_debug(1)) {
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static std::set<std::pair<IdString,IdString>> seen;
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if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt);
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}
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#endif
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for (auto bit : sigmap(conn.second)) {
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arrival_times[bit] = *jt;
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if (arrivals.size() > 1)
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jt++;
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}
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if (arrival)
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for (auto bit : sigmap(conn.second))
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arrival_times[bit] = arrival;
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}
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if (abc9_flop)
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@ -300,7 +321,7 @@ struct XAigerWriter
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RTLIL::Module* box_module = module->design->module(cell->type);
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log_assert(box_module);
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log_assert(box_module->attributes.count("\\abc9_box_id"));
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log_assert(box_module->attributes.count("\\abc9_box_id") || box_module->get_bool_attribute("\\abc9_flop"));
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auto r = box_ports.insert(cell->type);
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if (r.second) {
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@ -579,7 +600,11 @@ struct XAigerWriter
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RTLIL::Module* box_module = module->design->module(cell->type);
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log_assert(box_module);
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auto r = cell_cache.insert(cell->type);
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IdString derived_type = box_module->derive(box_module->design, cell->parameters);
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box_module = box_module->design->module(derived_type);
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log_assert(box_module);
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auto r = cell_cache.insert(derived_type);
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auto &v = r.first->second;
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if (r.second) {
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int box_inputs = 0, box_outputs = 0;
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@ -175,6 +175,7 @@ struct Abc9Pass : public ScriptPass
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std::stringstream exe_cmd;
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bool dff_mode, cleanup;
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std::string box_file;
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void clear_flags() YS_OVERRIDE
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{
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@ -182,6 +183,7 @@ struct Abc9Pass : public ScriptPass
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exe_cmd << "abc9_exe";
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dff_mode = false;
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cleanup = true;
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box_file.clear();
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -203,7 +205,7 @@ struct Abc9Pass : public ScriptPass
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std::string arg = args[argidx];
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if ((arg == "-exe" || arg == "-script" || arg == "-D" ||
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/* arg == "-S" || */ arg == "-lut" || arg == "-luts" ||
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arg == "-box" || arg == "-W") &&
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/*arg == "-box" ||*/ arg == "-W") &&
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argidx+1 < args.size()) {
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exe_cmd << " " << arg << " " << args[++argidx];
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continue;
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@ -222,6 +224,10 @@ struct Abc9Pass : public ScriptPass
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cleanup = false;
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continue;
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}
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if (arg == "-box" && argidx+1 < args.size()) {
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box_file = args[++argidx];
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continue;
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}
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if (arg == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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@ -251,11 +257,12 @@ struct Abc9Pass : public ScriptPass
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void script() YS_OVERRIDE
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{
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if (check_label("pre")) {
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run("abc9_ops -check");
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run("scc -set_attr abc9_scc_id {}");
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if (help_mode)
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run("abc9_ops -mark_scc -prep_xaiger [-dff]", "(option for -dff)");
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run("abc9_ops -mark_scc -prep_delays -prep_xaiger [-dff]", "(option for -dff)");
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else
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run("abc9_ops -mark_scc -prep_xaiger" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
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run("abc9_ops -mark_scc -prep_delays -prep_xaiger" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
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run("select -set abc9_holes A:abc9_holes");
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run("flatten -wb @abc9_holes");
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run("techmap @abc9_holes");
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@ -269,8 +276,9 @@ struct Abc9Pass : public ScriptPass
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if (check_label("map")) {
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if (help_mode) {
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run("foreach module in selection");
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run(" abc9_ops -write_box [<value from -box>|(null)] <abc-temp-dir>/input.box");
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run(" write_xaiger -map <abc-temp-dir>/input.sym <abc-temp-dir>/input.xaig");
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run(" abc9_exe -cwd <abc-temp-dir> [options]");
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run(" abc9_exe [options] -cwd <abc-temp-dir> -box <abc-temp-dir>/input.box");
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run(" read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig");
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run(" abc9_ops -reintegrate");
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}
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@ -296,6 +304,10 @@ struct Abc9Pass : public ScriptPass
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tempdir_name[0] = tempdir_name[4] = '_';
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tempdir_name = make_temp_dir(tempdir_name);
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if (box_file.empty())
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run(stringf("abc9_ops -write_box (null) %s/input.box", tempdir_name.c_str()));
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else
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run(stringf("abc9_ops -write_box %s %s/input.box", box_file.c_str(), tempdir_name.c_str()));
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run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
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int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs");
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@ -307,7 +319,7 @@ struct Abc9Pass : public ScriptPass
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active_design->scratchpad_get_int("write_xaiger.num_inputs"),
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num_outputs);
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if (num_outputs) {
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run(stringf("%s -cwd %s", exe_cmd.str().c_str(), tempdir_name.c_str()));
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run(stringf("%s -cwd %s -box %s/input.box", exe_cmd.str().c_str(), tempdir_name.c_str(), tempdir_name.c_str()));
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run(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name.c_str(), tempdir_name.c_str()));
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run("abc9_ops -reintegrate");
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}
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@ -510,9 +510,8 @@ struct Abc9ExePass : public Pass {
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}
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}
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// ABC expects a box file for XAIG
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if (box_file.empty())
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box_file = "+/dummy.box";
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log_cmd_error("abc9_exe '-box' option is mandatory.\n");
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rewrite_filename(box_file);
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if (!box_file.empty() && !is_absolute_path(box_file) && box_file[0] != '+')
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@ -23,6 +23,9 @@
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#include "kernel/utils.h"
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#include "kernel/celltypes.h"
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#define ABC9_FLOPS_BASE_ID 8000
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#define ABC9_DELAY_BASE_ID 9000
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -33,6 +36,110 @@ inline std::string remap_name(RTLIL::IdString abc9_name)
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return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
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}
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void check(RTLIL::Design *design)
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{
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dict<IdString,IdString> box_lookup;
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for (auto m : design->modules()) {
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if (m->name.begins_with("$paramod"))
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continue;
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auto flop = m->get_bool_attribute(ID(abc9_flop));
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auto it = m->attributes.find(ID(abc9_box_id));
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if (!flop) {
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if (it == m->attributes.end())
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continue;
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auto id = it->second.as_int();
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auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
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if (!r.second)
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log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
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log_id(m), id, log_id(r.first->second));
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}
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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for (const auto &port_name : m->ports) {
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auto w = m->wire(port_name);
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log_assert(w);
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input) {
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if (carry_in != IdString())
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log_error("Module '%s' contains more than one (* abc9_carry *) input port.\n", log_id(m));
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carry_in = port_name;
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}
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if (w->port_output) {
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if (carry_out != IdString())
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log_error("Module '%s' contains more than one (* abc9_carry *) output port.\n", log_id(m));
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carry_out = port_name;
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}
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}
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auto it = w->attributes.find("\\abc9_arrival");
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if (it != w->attributes.end()) {
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int count = 0;
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if (it->second.flags == 0) {
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if (it->second.as_int() < 0)
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log_error("%s.%s has negative arrival value %d!\n", log_id(m), log_id(port_name),
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it->second.as_int());
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count++;
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}
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else
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for (const auto &tok : split_tokens(it->second.decode_string())) {
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if (tok.find_first_not_of("0123456789") != std::string::npos)
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log_error("%s.%s has non-integer arrival value '%s'!\n", log_id(m), log_id(port_name),
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tok.c_str());
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if (atoi(tok.c_str()) < 0)
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log_error("%s.%s has negative arrival value %s!\n", log_id(m), log_id(port_name),
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tok.c_str());
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count++;
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}
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if (count > 1 && count != GetSize(w))
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log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(m), log_id(port_name),
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GetSize(w), log_signal(it->second), count);
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}
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it = w->attributes.find("\\abc9_required");
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if (it != w->attributes.end()) {
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int count = 0;
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if (it->second.flags == 0) {
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if (it->second.as_int() < 0)
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log_error("%s.%s has negative required value %d!\n", log_id(m), log_id(port_name),
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it->second.as_int());
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count++;
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}
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else
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for (const auto &tok : split_tokens(it->second.decode_string())) {
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if (tok.find_first_not_of("0123456789") != std::string::npos)
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log_error("%s.%s has non-integer required value '%s'!\n", log_id(m), log_id(port_name),
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tok.c_str());
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if (atoi(tok.c_str()) < 0)
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log_error("%s.%s has negative required value %s!\n", log_id(m), log_id(port_name),
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tok.c_str());
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count++;
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}
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if (count > 1 && count != GetSize(w))
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log_error("%s.%s is %d bits wide but abc9_required = %s has %d value(s)!\n", log_id(m), log_id(port_name),
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GetSize(w), log_signal(it->second), count);
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}
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}
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if (carry_in != IdString() && carry_out == IdString())
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log_error("Module '%s' contains an (* abc9_carry *) input port but no output port.\n", log_id(m));
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an (* abc9_carry *) output port but no input port.\n", log_id(m));
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if (flop) {
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int num_outputs = 0;
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for (auto port_name : m->ports) {
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auto wire = m->wire(port_name);
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if (wire->port_output) num_outputs++;
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}
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if (num_outputs != 1)
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log_error("Module '%s' with (* abc9_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
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}
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}
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}
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void mark_scc(RTLIL::Module *module)
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{
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// For every unique SCC found, (arbitrarily) find the first
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@ -169,13 +276,11 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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continue;
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auto inst_module = module->design->module(cell->type);
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bool abc9_box = inst_module && inst_module->attributes.count("\\abc9_box_id");
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bool abc9_flop = false;
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if (abc9_box) {
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abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
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if (abc9_flop && !dff)
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continue;
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bool abc9_flop = inst_module && inst_module->get_bool_attribute("\\abc9_flop");
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if (abc9_flop && !dff)
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continue;
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if ((inst_module && inst_module->attributes.count("\\abc9_box_id")) || abc9_flop) {
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auto r = box_ports.insert(cell->type);
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if (r.second) {
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// Make carry in the last PI, and carry out the last PO
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@ -185,25 +290,15 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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auto w = inst_module->wire(port_name);
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log_assert(w);
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input) {
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if (carry_in != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(inst_module));
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log_assert(w->port_input != w->port_output);
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if (w->port_input)
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carry_in = port_name;
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}
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if (w->port_output) {
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if (carry_out != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(inst_module));
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else if (w->port_output)
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carry_out = port_name;
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}
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}
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else
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r.first->second.push_back(port_name);
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}
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if (carry_in != IdString() && carry_out == IdString())
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log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(inst_module));
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if (carry_in == IdString() && carry_out != IdString())
|
||||
log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(inst_module));
|
||||
if (carry_in != IdString()) {
|
||||
r.first->second.push_back(carry_in);
|
||||
r.first->second.push_back(carry_out);
|
||||
|
|
@ -266,22 +361,25 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
|
|||
log_assert(cell);
|
||||
|
||||
RTLIL::Module* box_module = design->module(cell->type);
|
||||
if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
|
||||
if (!box_module || (!box_module->attributes.count("\\abc9_box_id") && !box_module->get_bool_attribute("\\abc9_flop")))
|
||||
continue;
|
||||
|
||||
cell->attributes["\\abc9_box_seq"] = box_count++;
|
||||
|
||||
IdString derived_name = box_module->derive(design, cell->parameters);
|
||||
box_module = design->module(derived_name);
|
||||
IdString derived_type = box_module->derive(design, cell->parameters);
|
||||
box_module = design->module(derived_type);
|
||||
|
||||
auto r = cell_cache.insert(derived_name);
|
||||
auto r = cell_cache.insert(derived_type);
|
||||
auto &holes_cell = r.first->second;
|
||||
if (r.second) {
|
||||
if (box_module->has_processes())
|
||||
Pass::call_on_module(design, box_module, "proc");
|
||||
|
||||
if (box_module->get_bool_attribute("\\whitebox")) {
|
||||
holes_cell = holes_module->addCell(cell->name, derived_name);
|
||||
holes_cell = holes_module->addCell(cell->name, derived_type);
|
||||
|
||||
if (box_module->has_processes())
|
||||
Pass::call_on_module(design, box_module, "proc");
|
||||
|
||||
int box_inputs = 0;
|
||||
for (auto port_name : box_ports.at(cell->type)) {
|
||||
|
|
@ -303,7 +401,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
|
|||
}
|
||||
}
|
||||
else if (w->port_output)
|
||||
conn = holes_module->addWire(stringf("%s.%s", derived_name.c_str(), log_id(port_name)), GetSize(w));
|
||||
conn = holes_module->addWire(stringf("%s.%s", derived_type.c_str(), log_id(port_name)), GetSize(w));
|
||||
}
|
||||
|
||||
// For flops only, create an extra 1-bit input that drives a new wire
|
||||
|
|
@ -342,6 +440,169 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
|
|||
}
|
||||
}
|
||||
|
||||
void prep_delays(RTLIL::Design *design)
|
||||
{
|
||||
std::set<int> delays;
|
||||
pool<Module*> flops;
|
||||
std::vector<Cell*> cells;
|
||||
dict<IdString,dict<IdString,std::vector<int>>> requireds_cache;
|
||||
for (auto module : design->selected_modules()) {
|
||||
if (module->processes.size() > 0) {
|
||||
log("Skipping module %s as it contains processes.\n", log_id(module));
|
||||
continue;
|
||||
}
|
||||
|
||||
cells.clear();
|
||||
for (auto cell : module->cells()) {
|
||||
if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_), ID($__ABC9_DELAY)))
|
||||
continue;
|
||||
|
||||
RTLIL::Module* inst_module = module->design->module(cell->type);
|
||||
if (!inst_module)
|
||||
continue;
|
||||
if (!inst_module->get_blackbox_attribute())
|
||||
continue;
|
||||
if (inst_module->get_bool_attribute(ID(abc9_flop))) {
|
||||
IdString derived_type = inst_module->derive(design, cell->parameters);
|
||||
inst_module = design->module(derived_type);
|
||||
log_assert(inst_module);
|
||||
flops.insert(inst_module);
|
||||
continue; // because all flop required times
|
||||
// will be captured in the flop box
|
||||
}
|
||||
if (inst_module->attributes.count(ID(abc9_box_id)))
|
||||
continue;
|
||||
cells.emplace_back(cell);
|
||||
}
|
||||
|
||||
delays.clear();
|
||||
for (auto cell : cells) {
|
||||
RTLIL::Module* inst_module = module->design->module(cell->type);
|
||||
log_assert(inst_module);
|
||||
auto &cell_requireds = requireds_cache[cell->type];
|
||||
for (auto &conn : cell->connections_) {
|
||||
auto port_wire = inst_module->wire(conn.first);
|
||||
if (!port_wire->port_input)
|
||||
continue;
|
||||
|
||||
auto r = cell_requireds.insert(conn.first);
|
||||
auto &requireds = r.first->second;
|
||||
if (r.second) {
|
||||
auto it = port_wire->attributes.find("\\abc9_required");
|
||||
if (it == port_wire->attributes.end())
|
||||
continue;
|
||||
if (it->second.flags == 0) {
|
||||
int delay = it->second.as_int();
|
||||
delays.insert(delay);
|
||||
requireds.emplace_back(delay);
|
||||
}
|
||||
else
|
||||
for (const auto &tok : split_tokens(it->second.decode_string())) {
|
||||
int delay = atoi(tok.c_str());
|
||||
delays.insert(delay);
|
||||
requireds.push_back(delay);
|
||||
}
|
||||
}
|
||||
|
||||
if (requireds.empty())
|
||||
continue;
|
||||
|
||||
SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
|
||||
auto it = requireds.begin();
|
||||
for (int i = 0; i < GetSize(conn.second); ++i) {
|
||||
#ifndef NDEBUG
|
||||
if (ys_debug(1)) {
|
||||
static std::set<std::pair<IdString,IdString>> seen;
|
||||
if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]);
|
||||
}
|
||||
#endif
|
||||
auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
|
||||
box->setPort(ID(I), conn.second[i]);
|
||||
box->setPort(ID(O), O[i]);
|
||||
box->setParam(ID(DELAY), *it);
|
||||
if (requireds.size() > 1)
|
||||
it++;
|
||||
conn.second[i] = O[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
std::stringstream ss;
|
||||
bool first = true;
|
||||
for (auto d : delays) {
|
||||
if (first)
|
||||
first = false;
|
||||
else
|
||||
ss << " ";
|
||||
ss << d;
|
||||
}
|
||||
module->attributes[ID(abc9_delays)] = ss.str();
|
||||
}
|
||||
|
||||
int flops_id = ABC9_FLOPS_BASE_ID;
|
||||
std::stringstream ss;
|
||||
for (auto flop_module : flops) {
|
||||
int num_inputs = 0, num_outputs = 0;
|
||||
for (auto port_name : flop_module->ports) {
|
||||
auto wire = flop_module->wire(port_name);
|
||||
if (wire->port_input) num_inputs++;
|
||||
if (wire->port_output) num_outputs++;
|
||||
}
|
||||
log_assert(num_outputs == 1);
|
||||
|
||||
auto r = flop_module->attributes.insert(ID(abc9_box_id));
|
||||
if (r.second)
|
||||
r.first->second = flops_id++;
|
||||
|
||||
ss << log_id(flop_module) << " " << r.first->second.as_int();
|
||||
ss << " 1 " << num_inputs+1 << " " << num_outputs << std::endl;
|
||||
bool first = true;
|
||||
for (auto port_name : flop_module->ports) {
|
||||
auto wire = flop_module->wire(port_name);
|
||||
if (!wire->port_input)
|
||||
continue;
|
||||
if (first)
|
||||
first = false;
|
||||
else
|
||||
ss << " ";
|
||||
ss << wire->attributes.at("\\abc9_required", 0).as_int();
|
||||
}
|
||||
// Last input is 'abc9_ff.Q'
|
||||
ss << " 0" << std::endl << std::endl;
|
||||
}
|
||||
design->scratchpad_set_string("abc9_ops.box.flops", ss.str());
|
||||
}
|
||||
|
||||
void write_box(RTLIL::Module *module, const std::string &src, const std::string &dst) {
|
||||
std::ofstream ofs(dst);
|
||||
log_assert(ofs.is_open());
|
||||
|
||||
// Since ABC can only accept one box file, we have to copy
|
||||
// over the existing box file
|
||||
if (src != "(null)") {
|
||||
std::ifstream ifs(src);
|
||||
ofs << ifs.rdbuf() << std::endl;
|
||||
ifs.close();
|
||||
}
|
||||
|
||||
ofs << module->design->scratchpad_get_string("abc9_ops.box.flops");
|
||||
|
||||
auto it = module->attributes.find(ID(abc9_delays));
|
||||
if (it != module->attributes.end()) {
|
||||
for (const auto &tok : split_tokens(it->second.decode_string())) {
|
||||
int d = atoi(tok.c_str());
|
||||
ofs << "$__ABC9_DELAY@" << d << " " << ABC9_DELAY_BASE_ID + d << " 0 1 1" << std::endl;
|
||||
ofs << d << std::endl;
|
||||
}
|
||||
module->attributes.erase(it);
|
||||
}
|
||||
|
||||
if (ofs.tellp() == 0)
|
||||
ofs << "(dummy) 1 0 0 0";
|
||||
|
||||
ofs.close();
|
||||
}
|
||||
|
||||
void reintegrate(RTLIL::Module *module)
|
||||
{
|
||||
auto design = module->design;
|
||||
|
|
@ -363,37 +624,29 @@ void reintegrate(RTLIL::Module *module)
|
|||
continue;
|
||||
|
||||
auto r = box_ports.insert(m->name);
|
||||
if (r.second) {
|
||||
// Make carry in the last PI, and carry out the last PO
|
||||
// since ABC requires it this way
|
||||
IdString carry_in, carry_out;
|
||||
for (const auto &port_name : m->ports) {
|
||||
auto w = m->wire(port_name);
|
||||
log_assert(w);
|
||||
if (w->get_bool_attribute("\\abc9_carry")) {
|
||||
if (w->port_input) {
|
||||
if (carry_in != IdString())
|
||||
log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
|
||||
carry_in = port_name;
|
||||
}
|
||||
if (w->port_output) {
|
||||
if (carry_out != IdString())
|
||||
log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(m));
|
||||
carry_out = port_name;
|
||||
}
|
||||
}
|
||||
else
|
||||
r.first->second.push_back(port_name);
|
||||
}
|
||||
if (!r.second)
|
||||
continue;
|
||||
|
||||
if (carry_in != IdString() && carry_out == IdString())
|
||||
log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
|
||||
if (carry_in == IdString() && carry_out != IdString())
|
||||
log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
|
||||
if (carry_in != IdString()) {
|
||||
r.first->second.push_back(carry_in);
|
||||
r.first->second.push_back(carry_out);
|
||||
// Make carry in the last PI, and carry out the last PO
|
||||
// since ABC requires it this way
|
||||
IdString carry_in, carry_out;
|
||||
for (const auto &port_name : m->ports) {
|
||||
auto w = m->wire(port_name);
|
||||
log_assert(w);
|
||||
if (w->get_bool_attribute("\\abc9_carry")) {
|
||||
log_assert(w->port_input != w->port_output);
|
||||
if (w->port_input)
|
||||
carry_in = port_name;
|
||||
else if (w->port_output)
|
||||
carry_out = port_name;
|
||||
}
|
||||
else
|
||||
r.first->second.push_back(port_name);
|
||||
}
|
||||
|
||||
if (carry_in != IdString()) {
|
||||
r.first->second.push_back(carry_in);
|
||||
r.first->second.push_back(carry_out);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -465,16 +718,6 @@ void reintegrate(RTLIL::Module *module)
|
|||
}
|
||||
|
||||
if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) {
|
||||
// Convert buffer into direct connection
|
||||
if (mapped_cell->type == ID($lut) &&
|
||||
GetSize(mapped_cell->getPort(ID::A)) == 1 &&
|
||||
mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
|
||||
SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name));
|
||||
SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name));
|
||||
module->connect(my_y, my_a);
|
||||
log_abort();
|
||||
continue;
|
||||
}
|
||||
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
|
||||
cell->parameters = mapped_cell->parameters;
|
||||
cell->attributes = mapped_cell->attributes;
|
||||
|
|
@ -506,12 +749,27 @@ void reintegrate(RTLIL::Module *module)
|
|||
}
|
||||
else {
|
||||
RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
|
||||
log_assert(existing_cell);
|
||||
if (!existing_cell)
|
||||
log_error("Cannot find existing box cell with name '%s' in original design.\n", log_id(mapped_cell));
|
||||
|
||||
if (existing_cell->type == ID($__ABC9_DELAY)) {
|
||||
SigBit I = mapped_cell->getPort(ID(i));
|
||||
SigBit O = mapped_cell->getPort(ID(o));
|
||||
if (I.wire)
|
||||
I.wire = module->wires_.at(remap_name(I.wire->name));
|
||||
log_assert(O.wire);
|
||||
O.wire = module->wires_.at(remap_name(O.wire->name));
|
||||
module->connect(O, I);
|
||||
continue;
|
||||
}
|
||||
|
||||
#ifndef NDEBUG
|
||||
RTLIL::Module* box_module = design->module(existing_cell->type);
|
||||
auto it = box_module->attributes.find(ID(abc9_box_id));
|
||||
log_assert(it != box_module->attributes.end());
|
||||
log_assert(mapped_cell->type == stringf("$__boxid%d", it->second.as_int()));
|
||||
IdString derived_type = box_module->derive(design, existing_cell->parameters);
|
||||
RTLIL::Module* derived_module = design->module(derived_type);
|
||||
log_assert(derived_module);
|
||||
log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
|
||||
#endif
|
||||
mapped_cell->type = existing_cell->type;
|
||||
|
||||
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
|
||||
|
|
@ -729,6 +987,14 @@ struct Abc9OpsPass : public Pass {
|
|||
log("mapping, and is expected to be called in conjunction with other operations from\n");
|
||||
log("the `abc9' script pass. Only fully-selected modules are supported.\n");
|
||||
log("\n");
|
||||
log(" -check\n");
|
||||
log(" check that the design is valid, e.g. (* abc9_box_id *) values are unique,\n");
|
||||
log(" (* abc9_carry *) is only given for one input/output port, etc.\n");
|
||||
log("\n");
|
||||
log(" -prep_delays\n");
|
||||
log(" insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");
|
||||
log(" certain delays, e.g. (* abc9_required *) values.\n");
|
||||
log("\n");
|
||||
log(" -mark_scc\n");
|
||||
log(" for an arbitrarily chosen cell in each unique SCC of each selected module\n");
|
||||
log(" (tagged with an (* abc9_scc_id = <int> *) attribute), temporarily mark all\n");
|
||||
|
|
@ -749,6 +1015,10 @@ struct Abc9OpsPass : public Pass {
|
|||
log(" compute the clock domain and initial value of each flop in the design.\n");
|
||||
log(" process the '$holes' module to support clock-enable functionality.\n");
|
||||
log("\n");
|
||||
log(" -write_box (<src>|(null)) <dst>\n");
|
||||
log(" copy the existing box file from <src> (skip if '(null)') and append any\n");
|
||||
log(" new box definitions.\n");
|
||||
log("\n");
|
||||
log(" -reintegrate\n");
|
||||
log(" for each selected module, re-intergrate the module '<module-name>$abc9'\n");
|
||||
log(" by first recovering ABC9 boxes, and then stitching in the remaining primary\n");
|
||||
|
|
@ -759,15 +1029,22 @@ struct Abc9OpsPass : public Pass {
|
|||
{
|
||||
log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
|
||||
|
||||
bool check_mode = false;
|
||||
bool prep_delays_mode = false;
|
||||
bool mark_scc_mode = false;
|
||||
bool prep_dff_mode = false;
|
||||
bool prep_xaiger_mode = false;
|
||||
bool reintegrate_mode = false;
|
||||
bool dff_mode = false;
|
||||
std::string write_box_src, write_box_dst;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
std::string arg = args[argidx];
|
||||
if (arg == "-check") {
|
||||
check_mode = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-mark_scc") {
|
||||
mark_scc_mode = true;
|
||||
continue;
|
||||
|
|
@ -780,6 +1057,17 @@ struct Abc9OpsPass : public Pass {
|
|||
prep_xaiger_mode = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-prep_delays") {
|
||||
prep_delays_mode = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-write_box" && argidx+2 < args.size()) {
|
||||
write_box_src = args[++argidx];
|
||||
write_box_dst = args[++argidx];
|
||||
rewrite_filename(write_box_src);
|
||||
rewrite_filename(write_box_dst);
|
||||
continue;
|
||||
}
|
||||
if (arg == "-reintegrate") {
|
||||
reintegrate_mode = true;
|
||||
continue;
|
||||
|
|
@ -792,12 +1080,17 @@ struct Abc9OpsPass : public Pass {
|
|||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
if (!(mark_scc_mode || prep_dff_mode || reintegrate_mode))
|
||||
log_cmd_error("At least one of -mark_scc, -prep_{xaiger,dff}, -reintegrate must be specified.\n");
|
||||
if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || !write_box_src.empty() || reintegrate_mode))
|
||||
log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff}, -write_box, -reintegrate must be specified.\n");
|
||||
|
||||
if (dff_mode && !prep_xaiger_mode)
|
||||
log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n");
|
||||
|
||||
if (check_mode)
|
||||
check(design);
|
||||
if (prep_delays_mode)
|
||||
prep_delays(design);
|
||||
|
||||
for (auto mod : design->selected_modules()) {
|
||||
if (mod->get_bool_attribute("\\abc9_holes"))
|
||||
continue;
|
||||
|
|
@ -810,6 +1103,8 @@ struct Abc9OpsPass : public Pass {
|
|||
if (!design->selected_whole_module(mod))
|
||||
log_error("Can't handle partially selected module %s!\n", log_id(mod));
|
||||
|
||||
if (!write_box_src.empty())
|
||||
write_box(mod, write_box_src, write_box_dst);
|
||||
if (mark_scc_mode)
|
||||
mark_scc(mod);
|
||||
if (prep_dff_mode)
|
||||
|
|
|
|||
|
|
@ -29,4 +29,3 @@ $(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
|
|||
$(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/cells.lib))
|
||||
$(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/dummy.box))
|
||||
|
|
|
|||
|
|
@ -1 +0,0 @@
|
|||
(dummy) 1 0 0 0
|
||||
|
|
@ -33,6 +33,11 @@ endmodule
|
|||
module \$__ABC9_FF_ (input D, output Q);
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id = (9000+DELAY) *)
|
||||
module \$__ABC9_DELAY (input I, output O);
|
||||
parameter DELAY = 0;
|
||||
endmodule
|
||||
|
||||
// Box to emulate async behaviour of FDC*
|
||||
(* abc9_box_id = 1000, lib_whitebox *)
|
||||
module \$__ABC9_ASYNC0 (input A, S, output Y);
|
||||
|
|
|
|||
|
|
@ -62,67 +62,6 @@ $__ABC9_ASYNC1 1001 1 2 1
|
|||
#A S
|
||||
0 764 # Y
|
||||
|
||||
# Flop boxes:
|
||||
# * Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
|
||||
# * Exception: $abc9_currQ is a special input (located last) necessary for clock-enable functionality
|
||||
|
||||
# Box 1100 : FDRE
|
||||
# name ID w/b ins outs
|
||||
FDRE 1100 1 5 1
|
||||
#C CE D R $abc9_currQ
|
||||
#0 109 -46 404 0
|
||||
0 109 0 404 0 # Q (-46ps Tsu clamped to 0)
|
||||
|
||||
# Box 1101 : FDRE_1
|
||||
# name ID w/b ins outs
|
||||
FDRE_1 1101 1 5 1
|
||||
#C CE D R $abc9_currQ
|
||||
#0 109 -46 404 0
|
||||
0 109 0 404 0 # Q (-46ps Tsu clamped to 0)
|
||||
|
||||
# Box 1102 : FDSE
|
||||
# name ID w/b ins outs
|
||||
FDSE 1102 1 5 1
|
||||
#C CE D R $abc9_currQ
|
||||
#0 109 -46 404 0
|
||||
0 109 0 404 0 # Q (-46ps Tsu clamped to 0)
|
||||
|
||||
# Box 1103 : FDSE_1
|
||||
# name ID w/b ins outs
|
||||
FDSE_1 1103 1 5 1
|
||||
#C CE D R $abc9_currQ
|
||||
#0 109 -46 404 0
|
||||
0 109 0 404 0 # Q (-46ps Tsu clamped to 0)
|
||||
|
||||
# Box 1104 : FDCE
|
||||
# name ID w/b ins outs
|
||||
FDCE 1104 1 5 1
|
||||
#C CE CLR D $abc9_currQ
|
||||
#0 109 764 -46 0
|
||||
0 109 764 0 0 # Q (-46ps Tsu clamped to 0)
|
||||
|
||||
# Box 1105 : FDCE_1
|
||||
# name ID w/b ins outs
|
||||
FDCE_1 1105 1 5 1
|
||||
#C CE CLR D $abc9_currQ
|
||||
#0 109 764 -46 0
|
||||
0 109 764 0 0 # Q (-46ps Tsu clamped to 0)
|
||||
|
||||
# Box 1106 : FDPE
|
||||
# name ID w/b ins outs
|
||||
FDPE 1106 1 5 1
|
||||
#C CE D PRE $abc9_currQ
|
||||
#0 109 -46 764 0
|
||||
0 109 0 764 0 # Q (-46ps Tsu clamped to 0)
|
||||
|
||||
# Box 1107 : FDPE_1
|
||||
# name ID w/b ins outs
|
||||
FDPE_1 1107 1 5 1
|
||||
#C CE D PRE $abc9_currQ
|
||||
#0 109 -46 764 0
|
||||
0 109 0 764 0 # Q (-46ps Tsu clamped to 0)
|
||||
|
||||
# Box 2000 : $__ABC9_LUT6
|
||||
# (private cell to emulate async behaviour of LUTRAMs)
|
||||
# SLICEM/A6LUT
|
||||
|
|
|
|||
|
|
@ -325,17 +325,20 @@ endmodule
|
|||
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
|
||||
|
||||
(* abc9_box_id=1100, lib_whitebox, abc9_flop *)
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDRE (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D,
|
||||
(* invertible_pin = "IS_R_INVERTED" *)
|
||||
(* abc9_required=404 *)
|
||||
input R
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
|
|
@ -349,30 +352,38 @@ module FDRE (
|
|||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1101, lib_whitebox, abc9_flop *)
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDRE_1 (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
input CE, D, R
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D,
|
||||
(* abc9_required=404 *)
|
||||
input R
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1102, lib_whitebox, abc9_flop *)
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDSE (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D,
|
||||
(* invertible_pin = "IS_S_INVERTED" *)
|
||||
(* abc9_required=404 *)
|
||||
input S
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
|
|
@ -386,13 +397,18 @@ module FDSE (
|
|||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1103, lib_whitebox, abc9_flop *)
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDSE_1 (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
input CE, D, S
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D,
|
||||
(* abc9_required=404 *)
|
||||
input S
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
initial Q <= INIT;
|
||||
|
|
@ -405,6 +421,7 @@ module FDRSE (
|
|||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
(* invertible_pin = "IS_CE_INVERTED" *)
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
input D,
|
||||
|
|
@ -434,17 +451,20 @@ module FDRSE (
|
|||
Q <= d;
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1104, lib_whitebox, abc9_flop *)
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDCE (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
(* invertible_pin = "IS_CLR_INVERTED" *)
|
||||
(* abc9_required=764 *)
|
||||
input CLR,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
|
|
@ -460,30 +480,38 @@ module FDCE (
|
|||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1105, lib_whitebox, abc9_flop *)
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDCE_1 (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
input CE, D, CLR
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
(* abc9_required=764 *)
|
||||
input CLR,
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1106, lib_whitebox, abc9_flop *)
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDPE (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D,
|
||||
(* invertible_pin = "IS_PRE_INVERTED" *)
|
||||
(* abc9_required=764 *)
|
||||
input PRE
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
|
|
@ -499,13 +527,18 @@ module FDPE (
|
|||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1107, lib_whitebox, abc9_flop *)
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module FDPE_1 (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
input CE, D, PRE
|
||||
(* abc9_required=109 *)
|
||||
input CE,
|
||||
//(* abc9_required=-46 *) // Negative required times not currently supported
|
||||
input D,
|
||||
(* abc9_required=764 *)
|
||||
input PRE
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
initial Q <= INIT;
|
||||
|
|
@ -1120,15 +1153,33 @@ module RAM16X1D_1 (
|
|||
endmodule
|
||||
|
||||
module RAM32X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
|
||||
(* abc9_arrival=1188 *)
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
(* abc9_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
(* abc9_required=453 *)
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
(* abc9_required=654 *)
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
|
||||
(* abc9_required=245 *)
|
||||
input A0,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/clBLM_R.sdf#L798
|
||||
(* abc9_required=208 *)
|
||||
input A1,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
|
||||
(* abc9_required=147 *)
|
||||
input A2,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
|
||||
(* abc9_required=68 *)
|
||||
input A3,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
|
||||
(* abc9_required=66 *)
|
||||
input A4,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
|
||||
);
|
||||
parameter INIT = 32'h0;
|
||||
|
|
@ -1143,15 +1194,33 @@ module RAM32X1D (
|
|||
endmodule
|
||||
|
||||
module RAM32X1D_1 (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
|
||||
(* abc9_arrival=1188 *)
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
(* abc9_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
(* abc9_required=453 *)
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
(* abc9_required=654 *)
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
|
||||
(* abc9_required=245 *)
|
||||
input A0,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/clBLM_R.sdf#L798
|
||||
(* abc9_required=208 *)
|
||||
input A1,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
|
||||
(* abc9_required=147 *)
|
||||
input A2,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
|
||||
(* abc9_required=68 *)
|
||||
input A3,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
|
||||
(* abc9_required=66 *)
|
||||
input A4,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
|
||||
);
|
||||
parameter INIT = 32'h0;
|
||||
|
|
@ -1166,15 +1235,36 @@ module RAM32X1D_1 (
|
|||
endmodule
|
||||
|
||||
module RAM64X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
(* abc9_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
(* abc9_required=453 *)
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
(* abc9_required=654 *)
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4, A5,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
|
||||
(* abc9_required=362 *)
|
||||
input A0,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
|
||||
(* abc9_required=245 *)
|
||||
input A1,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
|
||||
(* abc9_required=208 *)
|
||||
input A2,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
|
||||
(* abc9_required=147 *)
|
||||
input A3,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
|
||||
(* abc9_required=68 *)
|
||||
input A4,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
|
||||
(* abc9_required=66 *)
|
||||
input A5,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
|
||||
);
|
||||
parameter INIT = 64'h0;
|
||||
|
|
@ -1189,15 +1279,36 @@ module RAM64X1D (
|
|||
endmodule
|
||||
|
||||
module RAM64X1D_1 (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
(* abc9_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
(* abc9_required=453 *)
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
(* abc9_required=654 *)
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4, A5,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
|
||||
(* abc9_required=362 *)
|
||||
input A0,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
|
||||
(* abc9_required=245 *)
|
||||
input A1,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
|
||||
(* abc9_required=208 *)
|
||||
input A2,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
|
||||
(* abc9_required=147 *)
|
||||
input A3,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
|
||||
(* abc9_required=68 *)
|
||||
input A4,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
|
||||
(* abc9_required=66 *)
|
||||
input A5,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
|
||||
);
|
||||
parameter INIT = 64'h0;
|
||||
|
|
@ -1212,16 +1323,23 @@ module RAM64X1D_1 (
|
|||
endmodule
|
||||
|
||||
module RAM128X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
|
||||
// plus 204ps to cross MUXF7
|
||||
(* abc9_arrival=1357 *)
|
||||
output DPO, SPO,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
|
||||
// plus 208ps to cross MUXF7
|
||||
(* abc9_arrival=1359 *)
|
||||
output DPO, SPO,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
|
||||
(* abc9_required=453 *)
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
(* abc9_required=654 *)
|
||||
input WE,
|
||||
input [6:0] A, DPRA
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
|
||||
(* abc9_required="616 362 245 208 147 68 66" *)
|
||||
input [6:0] A,
|
||||
input [6:0] DPRA
|
||||
);
|
||||
parameter INIT = 128'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
|
|
@ -1253,24 +1371,44 @@ endmodule
|
|||
// Multi port.
|
||||
|
||||
module RAM32M (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
|
||||
(* abc9_arrival=1188 *)
|
||||
(* abc9_arrival="1153 1188" *)
|
||||
output [1:0] DOA,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
|
||||
(* abc9_arrival=1187 *)
|
||||
(* abc9_arrival="1161 1187" *)
|
||||
output [1:0] DOB,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
|
||||
(* abc9_arrival=1180 *)
|
||||
(* abc9_arrival="1158 1180" *)
|
||||
output [1:0] DOC,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
|
||||
(* abc9_arrival=1190 *)
|
||||
(* abc9_arrival="1163 1190" *)
|
||||
output [1:0] DOD,
|
||||
input [4:0] ADDRA, ADDRB, ADDRC, ADDRD,
|
||||
input [1:0] DIA, DIB, DIC, DID,
|
||||
input [4:0] ADDRA, ADDRB, ADDRC,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792-L802
|
||||
(* abc9_required="245 208 147 68 66" *)
|
||||
input [4:0] ADDRD,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
|
||||
(* abc9_required="453 384" *)
|
||||
input [1:0] DIA,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
|
||||
(* abc9_required="461 354" *)
|
||||
input [1:0] DIB,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
|
||||
(* abc9_required="457 375" *)
|
||||
input [1:0] DIC,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
|
||||
(* abc9_required="310 334" *)
|
||||
input [1:0] DID,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
input WE
|
||||
input WCLK,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
(* abc9_required=654 *)
|
||||
input WE
|
||||
);
|
||||
parameter [63:0] INIT_A = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_B = 64'h0000000000000000;
|
||||
|
|
@ -1367,22 +1505,38 @@ endmodule
|
|||
module RAM64M (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
|
||||
(* abc9_arrival=1153 *)
|
||||
output DOA,
|
||||
output DOA,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
(* abc9_arrival=1161 *)
|
||||
output DOB,
|
||||
output DOB,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
|
||||
(* abc9_arrival=1158 *)
|
||||
output DOC,
|
||||
output DOC,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
|
||||
(* abc9_arrival=1163 *)
|
||||
output DOD,
|
||||
input [5:0] ADDRA, ADDRB, ADDRC, ADDRD,
|
||||
input DIA, DIB, DIC, DID,
|
||||
output DOD,
|
||||
input [5:0] ADDRA, ADDRB, ADDRC,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
|
||||
(* abc9_required="362 245 208 147 68 66" *)
|
||||
input [5:0] ADDRD,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
|
||||
(* abc9_required=384 *)
|
||||
input DIA,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
|
||||
(* abc9_required=354 *)
|
||||
input DIB,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
|
||||
(* abc9_required=375 *)
|
||||
input DIC,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
|
||||
(* abc9_required=310 *)
|
||||
input DID,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
input WE
|
||||
input WCLK,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
(* abc9_required=654 *)
|
||||
input WE
|
||||
);
|
||||
parameter [63:0] INIT_A = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_B = 64'h0000000000000000;
|
||||
|
|
@ -2397,21 +2551,30 @@ module DSP48E1 (
|
|||
output reg MULTSIGNOUT,
|
||||
output OVERFLOW,
|
||||
`ifdef YOSYS
|
||||
(* abc9_arrival = \DSP48E1.P_arrival () *)
|
||||
(* abc9_arrival = \P.abc9_arrival () *)
|
||||
`endif
|
||||
output reg signed [47:0] P,
|
||||
output reg PATTERNBDETECT,
|
||||
output reg PATTERNDETECT,
|
||||
`ifdef YOSYS
|
||||
(* abc9_arrival = \DSP48E1.PCOUT_arrival () *)
|
||||
(* abc9_arrival = \PCOUT.abc9_arrival () *)
|
||||
`endif
|
||||
output [47:0] PCOUT,
|
||||
output UNDERFLOW,
|
||||
`ifdef YOSYS
|
||||
(* abc9_required = \A.abc9_required () *)
|
||||
`endif
|
||||
input signed [29:0] A,
|
||||
input [29:0] ACIN,
|
||||
input [3:0] ALUMODE,
|
||||
`ifdef YOSYS
|
||||
(* abc9_required = \B.abc9_required () *)
|
||||
`endif
|
||||
input signed [17:0] B,
|
||||
input [17:0] BCIN,
|
||||
`ifdef YOSYS
|
||||
(* abc9_required = \C.abc9_required () *)
|
||||
`endif
|
||||
input [47:0] C,
|
||||
input CARRYCASCIN,
|
||||
input CARRYIN,
|
||||
|
|
@ -2430,10 +2593,16 @@ module DSP48E1 (
|
|||
input CEM,
|
||||
input CEP,
|
||||
(* clkbuf_sink *) input CLK,
|
||||
`ifdef YOSYS
|
||||
(* abc9_required = \D.abc9_required () *)
|
||||
`endif
|
||||
input [24:0] D,
|
||||
input [4:0] INMODE,
|
||||
input MULTSIGNIN,
|
||||
input [6:0] OPMODE,
|
||||
`ifdef YOSYS
|
||||
(* abc9_required = \PCIN.abc9_required () *)
|
||||
`endif
|
||||
input [47:0] PCIN,
|
||||
input RSTA,
|
||||
input RSTALLCARRYIN,
|
||||
|
|
@ -2478,69 +2647,133 @@ module DSP48E1 (
|
|||
parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
|
||||
|
||||
`ifdef YOSYS
|
||||
function integer \DSP48E1.P_arrival ;
|
||||
function integer \A.abc9_required ;
|
||||
begin
|
||||
\DSP48E1.P_arrival = 0;
|
||||
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
|
||||
if (PREG != 0) \DSP48E1.P_arrival = 329;
|
||||
// Worst-case from CREG and MREG
|
||||
else if (CREG != 0) \DSP48E1.P_arrival = 1687;
|
||||
else if (MREG != 0) \DSP48E1.P_arrival = 1671;
|
||||
// Worst-case from AREG and BREG
|
||||
else if (AREG != 0) \DSP48E1.P_arrival = 2952;
|
||||
else if (BREG != 0) \DSP48E1.P_arrival = 2813;
|
||||
\A.abc9_required = 0;
|
||||
if (AREG != 0) \A.abc9_required = 254;
|
||||
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
|
||||
if (MREG != 0) \A.abc9_required = 1416;
|
||||
else if (PREG != 0) \A.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 3030 : 2739) ;
|
||||
end
|
||||
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
|
||||
if (PREG != 0) \DSP48E1.P_arrival = 329;
|
||||
// Worst-case from CREG and MREG
|
||||
else if (CREG != 0) \DSP48E1.P_arrival = 1687;
|
||||
else if (MREG != 0) \DSP48E1.P_arrival = 1671;
|
||||
// Worst-case from AREG, ADREG, BREG, DREG
|
||||
else if (AREG != 0) \DSP48E1.P_arrival = 3935;
|
||||
else if (DREG != 0) \DSP48E1.P_arrival = 3908;
|
||||
else if (ADREG != 0) \DSP48E1.P_arrival = 2958;
|
||||
else if (BREG != 0) \DSP48E1.P_arrival = 2813;
|
||||
// Worst-case from ADREG and MREG
|
||||
if (MREG != 0) \A.abc9_required = 2400;
|
||||
else if (ADREG != 0) \A.abc9_required = 1283;
|
||||
else if (PREG != 0) \A.abc9_required = 3723;
|
||||
else if (PREG != 0) \A.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 4014 : 3723) ;
|
||||
end
|
||||
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
|
||||
if (PREG != 0) \DSP48E1.P_arrival = 329;
|
||||
if (PREG != 0) \A.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1730 : 1441) ;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
function integer \B.abc9_required ;
|
||||
begin
|
||||
\B.abc9_required = 0;
|
||||
if (BREG != 0) \B.abc9_required = 324;
|
||||
else if (MREG != 0) \B.abc9_required = 1285;
|
||||
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
|
||||
if (PREG != 0) \B.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 2898 : 2608) ;
|
||||
end
|
||||
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
|
||||
if (PREG != 0) \B.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 2898 : 2608) ;
|
||||
end
|
||||
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
|
||||
if (PREG != 0) \B.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1718 : 1428) ;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
function integer \C.abc9_required ;
|
||||
begin
|
||||
\C.abc9_required = 0;
|
||||
if (CREG != 0) \C.abc9_required = 168;
|
||||
else if (PREG != 0) \C.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1534 : 1244) ;
|
||||
end
|
||||
endfunction
|
||||
function integer \D.abc9_required ;
|
||||
begin
|
||||
\D.abc9_required = 0;
|
||||
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
|
||||
end
|
||||
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
|
||||
if (DREG != 0) \D.abc9_required = 248;
|
||||
else if (ADREG != 0) \D.abc9_required = 1195;
|
||||
else if (MREG != 0) \D.abc9_required = 2310;
|
||||
else if (PREG != 0) \D.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 3925 : 3635) ;
|
||||
end
|
||||
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
function integer \PCIN.abc9_required ;
|
||||
begin
|
||||
\PCIN.abc9_required = 0;
|
||||
if (PREG != 0) \PCIN.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025) ;
|
||||
end
|
||||
endfunction
|
||||
function integer \P.abc9_arrival ;
|
||||
begin
|
||||
\P.abc9_arrival = 0;
|
||||
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
|
||||
if (PREG != 0) \P.abc9_arrival = 329;
|
||||
// Worst-case from CREG and MREG
|
||||
else if (CREG != 0) \P.abc9_arrival = 1687;
|
||||
else if (MREG != 0) \P.abc9_arrival = 1671;
|
||||
// Worst-case from AREG and BREG
|
||||
else if (AREG != 0) \P.abc9_arrival = 2952;
|
||||
else if (BREG != 0) \P.abc9_arrival = 2813;
|
||||
end
|
||||
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
|
||||
if (PREG != 0) \P.abc9_arrival = 329;
|
||||
// Worst-case from CREG and MREG
|
||||
else if (CREG != 0) \P.abc9_arrival = 1687;
|
||||
else if (MREG != 0) \P.abc9_arrival = 1671;
|
||||
// Worst-case from AREG, ADREG, BREG, DREG
|
||||
else if (AREG != 0) \P.abc9_arrival = 3935;
|
||||
else if (DREG != 0) \P.abc9_arrival = 3908;
|
||||
else if (ADREG != 0) \P.abc9_arrival = 2958;
|
||||
else if (BREG != 0) \P.abc9_arrival = 2813;
|
||||
end
|
||||
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
|
||||
if (PREG != 0) \P.abc9_arrival = 329;
|
||||
// Worst-case from AREG, BREG, CREG
|
||||
else if (CREG != 0) \DSP48E1.P_arrival = 1687;
|
||||
else if (AREG != 0) \DSP48E1.P_arrival = 1632;
|
||||
else if (BREG != 0) \DSP48E1.P_arrival = 1616;
|
||||
else if (CREG != 0) \P.abc9_arrival = 1687;
|
||||
else if (AREG != 0) \P.abc9_arrival = 1632;
|
||||
else if (BREG != 0) \P.abc9_arrival = 1616;
|
||||
end
|
||||
//else
|
||||
// $error("Invalid DSP48E1 configuration");
|
||||
end
|
||||
endfunction
|
||||
function integer \DSP48E1.PCOUT_arrival ;
|
||||
function integer \PCOUT.abc9_arrival ;
|
||||
begin
|
||||
\DSP48E1.PCOUT_arrival = 0;
|
||||
\PCOUT.abc9_arrival = 0;
|
||||
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
|
||||
if (PREG != 0) \DSP48E1.PCOUT_arrival = 435;
|
||||
if (PREG != 0) \PCOUT.abc9_arrival = 435;
|
||||
// Worst-case from CREG and MREG
|
||||
else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835;
|
||||
else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819;
|
||||
else if (CREG != 0) \PCOUT.abc9_arrival = 1835;
|
||||
else if (MREG != 0) \PCOUT.abc9_arrival = 1819;
|
||||
// Worst-case from AREG and BREG
|
||||
else if (AREG != 0) \DSP48E1.PCOUT_arrival = 3098;
|
||||
else if (BREG != 0) \DSP48E1.PCOUT_arrival = 2960;
|
||||
else if (AREG != 0) \PCOUT.abc9_arrival = 3098;
|
||||
else if (BREG != 0) \PCOUT.abc9_arrival = 2960;
|
||||
end
|
||||
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
|
||||
if (PREG != 0) \DSP48E1.PCOUT_arrival = 435;
|
||||
if (PREG != 0) \PCOUT.abc9_arrival = 435;
|
||||
// Worst-case from CREG and MREG
|
||||
else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835;
|
||||
else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819;
|
||||
else if (CREG != 0) \PCOUT.abc9_arrival = 1835;
|
||||
else if (MREG != 0) \PCOUT.abc9_arrival = 1819;
|
||||
// Worst-case from AREG, ADREG, BREG, DREG
|
||||
else if (AREG != 0) \DSP48E1.PCOUT_arrival = 4083;
|
||||
else if (DREG != 0) \DSP48E1.PCOUT_arrival = 4056;
|
||||
else if (BREG != 0) \DSP48E1.PCOUT_arrival = 2960;
|
||||
else if (ADREG != 0) \DSP48E1.PCOUT_arrival = 2859;
|
||||
else if (AREG != 0) \PCOUT.abc9_arrival = 4083;
|
||||
else if (DREG != 0) \PCOUT.abc9_arrival = 4056;
|
||||
else if (BREG != 0) \PCOUT.abc9_arrival = 2960;
|
||||
else if (ADREG != 0) \PCOUT.abc9_arrival = 2859;
|
||||
end
|
||||
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
|
||||
if (PREG != 0) \DSP48E1.PCOUT_arrival = 435;
|
||||
if (PREG != 0) \PCOUT.abc9_arrival = 435;
|
||||
// Worst-case from AREG, BREG, CREG
|
||||
else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835;
|
||||
else if (AREG != 0) \DSP48E1.PCOUT_arrival = 1780;
|
||||
else if (BREG != 0) \DSP48E1.PCOUT_arrival = 1765;
|
||||
else if (CREG != 0) \PCOUT.abc9_arrival = 1835;
|
||||
else if (AREG != 0) \PCOUT.abc9_arrival = 1780;
|
||||
else if (BREG != 0) \PCOUT.abc9_arrival = 1765;
|
||||
end
|
||||
//else
|
||||
// $error("Invalid DSP48E1 configuration");
|
||||
|
|
|
|||
|
|
@ -180,18 +180,58 @@ CELLS = [
|
|||
Cell('RAMB18E1', port_attrs={
|
||||
'CLKARDCLK': ['clkbuf_sink'],
|
||||
'CLKBWRCLK': ['clkbuf_sink'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143
|
||||
'DOADO': ['abc9_arrival=2454'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163
|
||||
'DOBDO': ['abc9_arrival=2454'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144
|
||||
'DOPADOP': ['abc9_arrival=2454'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164
|
||||
'DOPBDOP': ['abc9_arrival=2454'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13
|
||||
'ADDRARDADDR': ['abc9_required=566'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17
|
||||
'ADDRBWRADDR': ['abc9_required=566'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19
|
||||
'WEA': ['abc9_required=532'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21
|
||||
'WEBWE': ['abc9_required=532'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123
|
||||
'DIADI': ['abc9_required=737'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133
|
||||
'DIBDI': ['abc9_required=737'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125
|
||||
'DIPADIP': ['abc9_required=737'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135
|
||||
'DIPBDIP': ['abc9_required=737'],
|
||||
}),
|
||||
Cell('RAMB36E1', port_attrs={
|
||||
'CLKARDCLK': ['clkbuf_sink'],
|
||||
'CLKBWRCLK': ['clkbuf_sink'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143
|
||||
'DOADO': ['abc9_arrival=2454'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163
|
||||
'DOBDO': ['abc9_arrival=2454'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144
|
||||
'DOPADOP': ['abc9_arrival=2454'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164
|
||||
'DOPBDOP': ['abc9_arrival=2454'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13
|
||||
'ADDRARDADDR': ['abc9_required=566'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17
|
||||
'ADDRBWRADDR': ['abc9_required=566'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19
|
||||
'WEA': ['abc9_required=532'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21
|
||||
'WEBWE': ['abc9_required=532'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123
|
||||
'DIADI': ['abc9_required=737'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133
|
||||
'DIBDI': ['abc9_required=737'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125
|
||||
'DIPADIP': ['abc9_required=737'],
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135
|
||||
'DIPBDIP': ['abc9_required=737'],
|
||||
}),
|
||||
# Ultrascale.
|
||||
Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
||||
|
|
|
|||
|
|
@ -4518,13 +4518,21 @@ module RAMB18E1 (...);
|
|||
input RSTREGARSTREG;
|
||||
(* invertible_pin = "IS_RSTREGB_INVERTED" *)
|
||||
input RSTREGB;
|
||||
(* abc9_required=566 *)
|
||||
input [13:0] ADDRARDADDR;
|
||||
(* abc9_required=566 *)
|
||||
input [13:0] ADDRBWRADDR;
|
||||
(* abc9_required=737 *)
|
||||
input [15:0] DIADI;
|
||||
(* abc9_required=737 *)
|
||||
input [15:0] DIBDI;
|
||||
(* abc9_required=737 *)
|
||||
input [1:0] DIPADIP;
|
||||
(* abc9_required=737 *)
|
||||
input [1:0] DIPBDIP;
|
||||
(* abc9_required=532 *)
|
||||
input [1:0] WEA;
|
||||
(* abc9_required=532 *)
|
||||
input [3:0] WEBWE;
|
||||
endmodule
|
||||
|
||||
|
|
@ -4742,13 +4750,21 @@ module RAMB36E1 (...);
|
|||
input REGCEB;
|
||||
input INJECTDBITERR;
|
||||
input INJECTSBITERR;
|
||||
(* abc9_required=566 *)
|
||||
input [15:0] ADDRARDADDR;
|
||||
(* abc9_required=566 *)
|
||||
input [15:0] ADDRBWRADDR;
|
||||
(* abc9_required=737 *)
|
||||
input [31:0] DIADI;
|
||||
(* abc9_required=737 *)
|
||||
input [31:0] DIBDI;
|
||||
(* abc9_required=737 *)
|
||||
input [3:0] DIPADIP;
|
||||
(* abc9_required=737 *)
|
||||
input [3:0] DIPBDIP;
|
||||
(* abc9_required=532 *)
|
||||
input [3:0] WEA;
|
||||
(* abc9_required=532 *)
|
||||
input [7:0] WEBWE;
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue