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Move abc9.* constpad entries to Abc9Pass::on_register()

This commit is contained in:
Eddie Hung 2020-01-09 17:10:54 -08:00
parent dd718838bb
commit 67c9c41f7e
2 changed files with 37 additions and 35 deletions
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35
kernel/yosys.cc
View File

@ -524,41 +524,6 @@ void yosys_setup()
PyRun_SimpleString("import sys");
#endif
RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
RTLIL::constpad["abc9.script.default.fast"] = "&if {C} {W} {D} {R}";
// Based on ABC's &flow
RTLIL::constpad["abc9.script.flow"] = "&scorr; &sweep;" \
/* Round 1 */ \
"&unmap; &if {C} {W} {D} {R}; &mfs;" \
"&st; &dsdb;" \
"&unmap; &if {C} {W} {D} {R}; &mfs;" \
"&st; &syn2 -m -R 10; &dsdb;" \
"&blut -a -K 6;" \
"&unmap; &if {C} {W} {D} {R}; &mfs;" \
/* Round 2 */ \
"&st; &sopb;" \
"&unmap; &if {C} {W} {D} {R}; &mfs;" \
"&st; &dsdb;" \
"&unmap; &if {C} {W} {D} {R}; &mfs;" \
"&st; &syn2 -m -R 10; &dsdb;" \
"&blut -a -K 6;" \
"&unmap; &if {C} {W} {D} {R} -v; &mfs";
// Based on ABC's &flow2
RTLIL::constpad["abc9.script.flow2"] = "&scorr; &sweep;" \
/* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
"&load; &st; &sopb -R 10 -C 4; " \
/* Comm3 */ "&synch2 -K 6 -C 500; &if -m "/*"-E 5"*/" {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\
"&load";
// Based on ABC's &flow3
RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \
"&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\
"&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\
"&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\
"&mfs";
Pass::init_register();
yosys_design = new RTLIL::Design;
yosys_celltypes.setup();

37
passes/techmap/abc9.cc
View File

@ -735,6 +735,43 @@ clone_lut:
struct Abc9Pass : public Pass {
Abc9Pass() : Pass("abc9", "use ABC9 for technology mapping") { }
void on_register() YS_OVERRIDE
{
RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
RTLIL::constpad["abc9.script.default.fast"] = "&if {C} {W} {D} {R}";
// Based on ABC's &flow
RTLIL::constpad["abc9.script.flow"] = "&scorr; &sweep;" \
/* Round 1 */ \
"&unmap; &if {C} {W} {D} {R}; &mfs;" \
"&st; &dsdb;" \
"&unmap; &if {C} {W} {D} {R}; &mfs;" \
"&st; &syn2 -m -R 10; &dsdb;" \
"&blut -a -K 6;" \
"&unmap; &if {C} {W} {D} {R}; &mfs;" \
/* Round 2 */ \
"&st; &sopb;" \
"&unmap; &if {C} {W} {D} {R}; &mfs;" \
"&st; &dsdb;" \
"&unmap; &if {C} {W} {D} {R}; &mfs;" \
"&st; &syn2 -m -R 10; &dsdb;" \
"&blut -a -K 6;" \
"&unmap; &if {C} {W} {D} {R} -v; &mfs";
// Based on ABC's &flow2
RTLIL::constpad["abc9.script.flow2"] = "&scorr; &sweep;" \
/* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
"&load; &st; &sopb -R 10 -C 4; " \
/* Comm3 */ "&synch2 -K 6 -C 500; &if -m "/*"-E 5"*/" {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\
"&load";
// Based on ABC's &flow3
RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \
"&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\
"&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\
"&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\
"&mfs";
}
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|