mirror of https://github.com/YosysHQ/yosys.git
Cleanup abc9, update doc for -keepff option
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@ -250,7 +250,7 @@ struct abc9_output_filter
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void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string script_file, std::string exe_file,
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bool cleanup, vector<int> lut_costs, bool keepff, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
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const std::vector<RTLIL::Cell*> &/*cells*/, bool show_tempdir, std::string box_file, std::string lut_file,
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bool show_tempdir, std::string box_file, std::string lut_file,
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std::string wire_delay, bool nomfs
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)
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{
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@ -796,8 +796,8 @@ struct Abc9Pass : public Pass {
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log(" 2, 3, .. inputs.\n");
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log("\n");
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log(" -keepff\n");
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log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
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log(" them, for example for equivalence checking.)\n");
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log(" do not represent (* abc9_flop *) modules as boxes (and thus do not perform\n");
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log(" any form of sequential synthesis).\n");
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log("\n");
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log(" -nocleanup\n");
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log(" when this option is used, the temporary files created by this pass\n");
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@ -985,10 +985,9 @@ struct Abc9Pass : public Pass {
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typedef SigSpec clkdomain_t;
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dict<clkdomain_t, int> clk_to_mergeability;
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const std::vector<RTLIL::Cell*> all_cells = module->selected_cells();
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if (!keepff)
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for (auto cell : all_cells) {
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for (auto cell : module->selected_cells()) {
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auto inst_module = design->module(cell->type);
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if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop"))
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continue;
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@ -1017,7 +1016,7 @@ struct Abc9Pass : public Pass {
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design->selected_active_module = module->name.str();
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abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, keepff,
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delay_target, lutin_shared, fast_mode, all_cells, show_tempdir,
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delay_target, lutin_shared, fast_mode, show_tempdir,
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box_file, lut_file, wire_delay, nomfs);
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design->selected_active_module.clear();
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}
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