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@ -619,26 +619,90 @@ struct XAigerWriter
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// write_o_buffer(0);
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if (!box_list.empty() || !ff_bits.empty()) {
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RTLIL::Module *holes_module = module->design->addModule("$__holes__");
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log_assert(holes_module);
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dict<IdString, Cell*> cell_cache;
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int port_id = 1;
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int box_count = 0;
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for (auto cell : box_list) {
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RTLIL::Module* orig_box_module = module->design->module(cell->type);
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log_assert(orig_box_module);
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IdString derived_name = orig_box_module->derive(module->design, cell->parameters);
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RTLIL::Module* box_module = module->design->module(derived_name);
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if (box_module->has_processes())
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Pass::call_on_module(module->design, box_module, "proc");
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auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
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Cell *holes_cell = r.first->second;
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if (r.second && box_module->get_bool_attribute("\\whitebox")) {
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holes_cell = holes_module->addCell(cell->name, cell->type);
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holes_cell->parameters = cell->parameters;
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r.first->second = holes_cell;
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}
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int box_inputs = 0, box_outputs = 0;
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for (auto port_name : box_ports.at(cell->type)) {
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RTLIL::Wire *w = box_module->wire(port_name);
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log_assert(w);
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RTLIL::Wire *holes_wire;
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RTLIL::SigSpec port_sig;
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if (w->port_input)
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box_inputs += GetSize(w);
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if (w->port_output)
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for (int i = 0; i < GetSize(w); i++) {
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box_inputs++;
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holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
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if (!holes_wire) {
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holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
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holes_wire->port_input = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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}
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if (holes_cell)
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port_sig.append(holes_wire);
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}
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if (w->port_output) {
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box_outputs += GetSize(w);
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for (int i = 0; i < GetSize(w); i++) {
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if (GetSize(w) == 1)
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holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
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else
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holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
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holes_wire->port_output = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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if (holes_cell)
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port_sig.append(holes_wire);
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else
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holes_module->connect(holes_wire, State::S0);
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}
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}
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if (!port_sig.empty()) {
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if (r.second)
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holes_cell->setPort(w->name, port_sig);
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else
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holes_module->connect(holes_cell->getPort(w->name), port_sig);
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}
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}
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// For flops only, create an extra 1-bit input for abc9_ff.Q
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if (box_module->get_bool_attribute("\\abc9_flop"))
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// For flops only, create an extra 1-bit input that drives a new wire
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// called "<cell>.abc9_ff.Q" that is used below
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if (box_module->get_bool_attribute("\\abc9_flop")) {
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log_assert(holes_cell);
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box_inputs++;
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Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
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if (!holes_wire) {
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holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
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holes_wire->port_input = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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}
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Wire *w = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
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log_assert(w);
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holes_module->connect(w, holes_wire);
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}
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write_h_buffer(box_inputs);
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write_h_buffer(box_outputs);
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@ -690,27 +754,81 @@ struct XAigerWriter
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
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log_assert(holes_module);
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if (holes_module) {
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log_push();
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for (auto cell : holes_module->cells())
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if (!cell->type.in("$_NOT_", "$_AND_"))
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log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
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// NB: fixup_ports() will sort ports by name
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//holes_module->fixup_ports();
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holes_module->check();
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module->design->selection_stack.emplace_back(false);
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module->design->selection().select(holes_module);
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// Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
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// since boxes may contain parameters in which case `flatten` would have
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// created a new $paramod ...
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Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap");
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std::stringstream a_buffer;
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XAigerWriter writer(holes_module);
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writer.write_aiger(a_buffer, false /*ascii_mode*/);
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dict<SigSig, SigSig> replace;
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for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
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auto cell = it->second;
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if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
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"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
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SigBit D = cell->getPort("\\D");
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SigBit Q = cell->getPort("\\Q");
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// Remove the DFF cell from what needs to be a combinatorial box
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it = holes_module->cells_.erase(it);
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Wire *port;
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if (GetSize(Q.wire) == 1)
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port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
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else
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port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
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log_assert(port);
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// Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
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// in order to extract the combinatorial control logic that feeds the box
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// (i.e. clock enable, synchronous reset, etc.)
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replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
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// Since `flatten` above would have created wires named "<cell>.Q",
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// extract the pre-techmap cell name
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auto pos = Q.wire->name.str().rfind(".");
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log_assert(pos != std::string::npos);
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IdString driver = Q.wire->name.substr(0, pos);
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// And drive the signal that was previously driven by "DFF.Q" (typically
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// used to implement clock-enable functionality) with the "<cell>.abc9_ff.Q"
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// wire (which itself is driven an input port) we inserted above
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Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
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log_assert(currQ);
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holes_module->connect(Q, currQ);
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continue;
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}
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else if (!cell->type.in("$_NOT_", "$_AND_"))
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log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
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++it;
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}
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module->design->selection_stack.pop_back();
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for (auto &conn : holes_module->connections_) {
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auto it = replace.find(conn);
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if (it != replace.end())
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conn = it->second;
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}
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f << "a";
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buffer_str = a_buffer.str();
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buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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// Move into a new (temporary) design so that "clean" will only
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// operate (and run checks on) this one module
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RTLIL::Design *holes_design = new RTLIL::Design;
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module->design->modules_.erase(holes_module->name);
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holes_design->add(holes_module);
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Pass::call(holes_design, "opt -purge");
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std::stringstream a_buffer;
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XAigerWriter writer(holes_module);
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writer.write_aiger(a_buffer, false /*ascii_mode*/);
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delete holes_design;
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f << "a";
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std::string buffer_str = a_buffer.str();
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int32_t buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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log_pop();
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}
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}
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f << "h";
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@ -185,17 +185,17 @@ struct Abc9Pass : public ScriptPass
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void script() YS_OVERRIDE
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{
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run("abc9_ops -prep_holes");
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run("select -set abc9_holes A:abc9_holes");
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run("flatten -wb @abc9_holes");
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run("techmap @abc9_holes");
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run("scc -set_attr abc9_scc_id {}");
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run("abc9_ops -break_scc");
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run("abc9_ops -break_scc"/*" -prep_holes"*/);
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// run("select -set abc9_holes A:abc9_holes");
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// run("dump @abc9_holes");
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// run("flatten -wb @abc9_holes");
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// run("techmap @abc9_holes");
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run("aigmap");
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if (dff_mode)
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run("abc9_ops -prep_dff");
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run("opt -purge @abc9_holes");
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run("wbflip @abc9_holes");
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// run("opt -purge @abc9_holes");
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// run("wbflip @abc9_holes");
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auto selected_modules = active_design->selected_modules();
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active_design->selection_stack.emplace_back(false);
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