mirror of https://github.com/YosysHQ/yosys.git
Remove a few log_{push,pop}()
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4eaf415052
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@ -266,8 +266,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
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fprintf(f, "%s\n", abc9_script.c_str());
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fclose(f);
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log_push();
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int count_outputs = design->scratchpad_get_int("write_xaiger.num_outputs");
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log("Extracted %d AND gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
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design->scratchpad_get_int("write_xaiger.num_ands"),
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@ -645,8 +643,6 @@ clone_lut:
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//{
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// log("Don't call ABC as there is nothing to map.\n");
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//}
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log_pop();
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}
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struct Abc9MapPass : public Pass {
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@ -759,7 +755,6 @@ struct Abc9MapPass : public Pass {
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing ABC9_MAP pass (technology mapping using ABC9).\n");
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log_push();
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#ifdef ABCEXTERNAL
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std::string exe_file = ABCEXTERNAL;
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@ -913,8 +908,6 @@ struct Abc9MapPass : public Pass {
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delay_target, lutin_shared, fast_mode, all_cells, show_tempdir,
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box_file, lut_file, wire_delay, nomfs, tempdir_name);
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}
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log_pop();
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}
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} Abc9MapPass;
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@ -436,7 +436,6 @@ struct Abc9OpsPass : public Pass {
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
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log_push();
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bool break_scc_mode = false;
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bool unbreak_scc_mode = false;
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