riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

techmap: use +/techmap.v instead of an ad-hoc code generator.

This commit is contained in:
whitequark 2020-06-02 22:19:34 +00:00
parent 4b3f48a7ec
commit 68d747f767
3 changed files with 1 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
passes/techmap/.gitignore vendored
View File

@ -1 +0,0 @@
techmap.inc

12
passes/techmap/Makefile.inc
View File

@ -45,18 +45,6 @@ OBJS += passes/techmap/flowmap.o
OBJS += passes/techmap/extractinv.o
endif
GENFILES += passes/techmap/techmap.inc
passes/techmap/techmap.inc: techlibs/common/techmap.v
$(Q) mkdir -p $(dir $@)
$(P) echo "// autogenerated from $<" > $@.new
$(Q) echo "static char stdcells_code[] = {" >> $@.new
$(Q) od -v -td1 -An $< | $(SED) -e 's/[0-9][0-9]*/&,/g' >> $@.new
$(Q) echo "0};" >> $@.new
$(Q) mv $@.new $@
passes/techmap/techmap.o: passes/techmap/techmap.inc
ifeq ($(DISABLE_SPAWN),0)
TARGETS += $(PROGRAM_PREFIX)yosys-filterlib$(EXE)
EXTRA_OBJS += passes/techmap/filterlib.o

4
passes/techmap/techmap.cc
View File

@ -27,7 +27,6 @@
#include <string.h>
#include "simplemap.h"
#include "passes/techmap/techmap.inc"
YOSYS_NAMESPACE_BEGIN
@ -1282,8 +1281,7 @@ struct TechmapPass : public Pass {
RTLIL::Design *map = new RTLIL::Design;
if (map_files.empty()) {
std::istringstream f(stdcells_code);
Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend);
Frontend::frontend_call(map, nullptr, "+/techmap.v", verilog_frontend);
} else {
for (auto &fn : map_files)
if (fn.compare(0, 1, "%") == 0) {