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Merge pull request #2102 from YosysHQ/tests_fix
allow range for mux test
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4b3f48a7ec
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@ -35,6 +35,7 @@ proc
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equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 11 t:SB_LUT4
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select -assert-min 11 t:SB_LUT4
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select -assert-max 12 t:SB_LUT4
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select -assert-none t:SB_LUT4 %% t:* %D
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