mirror of https://github.com/YosysHQ/yosys.git
abc9: suppress warnings when no compatible + used flop boxes formed
This commit is contained in:
Eddie Hung
parent
cdd250ef16
commit
8d7b3c06b2
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@ -281,41 +281,52 @@ struct Abc9Pass : public ScriptPass
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if (check_label("dff", "(only if -dff)")) {
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if (dff_mode || help_mode) {
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run("abc9_ops -prep_dff_hier"); // derive all used (* abc9_flop *) modules,
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// create stubs in $abc9_unmap design
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// create stubs in $abc9_unmap design
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run("design -stash $abc9");
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run("design -copy-from $abc9 @$abc9_flops"); // copy derived modules in
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run("proc");
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run("wbflip");
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run("techmap");
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run("opt");
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if (!help_mode)
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active_design->scratchpad_unset("abc9_ops.prep_dff_map.did_something");
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run("abc9_ops -prep_dff_map"); // rewrite specify
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// select all $_DFF_[NP]_
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// then select all its fanins
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// then select all fanouts of all that
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// lastly remove $_DFF_[NP]_ cells
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run("setattr -set submod \"$abc9_flop\" t:$_DFF_?_ %ci* %co* t:$_DFF_?_ %d");
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run("submod");
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run("design -copy-to $abc9 *_$abc9_flop"); // copy submod out
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run("delete *_$abc9_flop");
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if (help_mode) {
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run("foreach module in design");
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run(" rename <module-name>_$abc9_flop _TECHMAP_REPLACE_");
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bool did_something = help_mode || active_design->scratchpad_get_bool("abc9_ops.prep_dff_map.did_something");
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if (did_something) {
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// select all $_DFF_[NP]_
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// then select all its fanins
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// then select all fanouts of all that
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// lastly remove $_DFF_[NP]_ cells
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run("setattr -set submod \"$abc9_flop\" t:$_DFF_?_ %ci* %co* t:$_DFF_?_ %d");
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run("submod");
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run("design -copy-to $abc9 *_$abc9_flop"); // copy submod out
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run("delete *_$abc9_flop");
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if (help_mode) {
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run("foreach module in design");
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run(" rename <module-name>_$abc9_flop _TECHMAP_REPLACE_");
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}
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else {
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// Rename all submod-s to _TECHMAP_REPLACE_ to inherit name + attrs
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for (auto module : active_design->selected_modules()) {
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active_design->selected_active_module = module->name.str();
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if (module->cell(stringf("%s_$abc9_flop", module->name.c_str())))
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run(stringf("rename %s_$abc9_flop _TECHMAP_REPLACE_", module->name.c_str()));
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}
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}
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run("design -stash $abc9_map");
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run("design -load $abc9");
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run("design -delete $abc9");
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run("select -unset $abc9_flops");
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run("techmap -wb -map %$abc9_map"); // techmap user design into submod + $_DFF_[NP]_
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run("design -delete $abc9_map");
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run("setattr -mod -set whitebox 1 -set abc9_flop 1 -set abc9_box 1 *_$abc9_flop");
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run("abc9_ops -prep_dff_unmap"); // implement $abc9_unmap design
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}
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else {
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// Rename all submod-s to _TECHMAP_REPLACE_ to inherit name + attrs
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for (auto module : active_design->selected_modules()) {
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active_design->selected_active_module = module->name.str();
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run(stringf("rename %s_$abc9_flop _TECHMAP_REPLACE_", module->name.c_str()));
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}
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run("design -load $abc9");
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run("design -delete $abc9");
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run("select -unset $abc9_flops");
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}
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run("design -stash $abc9_map");
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run("design -load $abc9");
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run("design -delete $abc9");
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run("select -unset $abc9_flops");
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run("abc9_ops -prep_dff_unmap"); // implement $abc9_unmap design
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run("techmap -map %$abc9_map"); // techmap user design into submod + $_DFF_[NP]_
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run("design -delete $abc9_map");
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run("setattr -mod -set whitebox 1 -set abc9_flop 1 -set abc9_box 1 *_$abc9_flop");
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}
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}
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@ -161,10 +161,23 @@ void prep_dff_hier(RTLIL::Design *design)
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void prep_dff_map(RTLIL::Design *design)
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{
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Design *unmap_design = saved_designs.at("$abc9_unmap");
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for (auto module : design->modules()) {
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vector<Cell*> specify_cells;
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SigBit D, Q;
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Cell* dff_cell = nullptr;
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// If module has a public name (i.e. not $paramod) and it doesn't exist
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// in the $abc9_unmap then it means only derived modules were
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// instantiated, so make this a blackbox
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if (module->name[0] == '\\' && !unmap_design->module(module->name.str() + "_$abc9_flop")) {
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module->makeblackbox();
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module->set_bool_attribute(ID::blackbox, false);
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module->set_bool_attribute(ID::whitebox, true);
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continue;
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}
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for (auto cell : module->cells())
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if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
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if (dff_cell)
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@ -185,6 +198,7 @@ void prep_dff_map(RTLIL::Design *design)
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log_warning("Module '%s' contains a %s cell with non-zero initial state -- this is not unsupported for ABC9 sequential synthesis. Treating as a blackbox.\n", log_id(module), log_id(cell->type));
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module->makeblackbox();
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module->set_bool_attribute(ID::blackbox, false);
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auto wire = module->addWire(ID(_TECHMAP_FAIL_));
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wire->set_bool_attribute(ID::keep);
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@ -215,19 +229,20 @@ void prep_dff_map(RTLIL::Design *design)
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D = w;
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}
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if (GetSize(specify_cells) == 0) {
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log_warning("Module '%s' marked (* abc9_flop *) contains no specify timing information.\n", log_id(module));
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}
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else {
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// Rewrite $specify cells that end with $_DFF_[NP]_.Q
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// to $_DFF_[NP]_.D since it will be moved into
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// the submodule
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for (auto cell : specify_cells) {
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auto DST = cell->getPort(ID::DST);
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DST.replace(Q, D);
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cell->setPort(ID::DST, DST);
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}
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if (GetSize(specify_cells) == 0)
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log_error("Module '%s' marked (* abc9_flop *) contains no specify timing information.\n", log_id(module));
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// Rewrite $specify cells that end with $_DFF_[NP]_.Q
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// to $_DFF_[NP]_.D since it will be moved into
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// the submodule
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for (auto cell : specify_cells) {
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auto DST = cell->getPort(ID::DST);
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DST.replace(Q, D);
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cell->setPort(ID::DST, DST);
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}
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design->scratchpad_set_bool("abc9_ops.prep_dff_map.did_something", true);
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continue_outer_loop: ;
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}
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}
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@ -14,6 +14,7 @@ endmodule
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EOT
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equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
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design -load postopt
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select -assert-count 6 t:FD*
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select -assert-count 6 c:fd2 c:fd3 c:fd4 c:fd6 c:fd7 c:fd8
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@ -32,6 +33,7 @@ endmodule
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EOT
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equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
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design -load postopt
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select -assert-count 4 t:FD*
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select -assert-count 4 c:fd3 c:fd4 c:fd7 c:fd8
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@ -54,6 +56,6 @@ logger -expect warning "Module 'FDSE' contains a \$_DFF_P_ cell .*" 1
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logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$_DFF_N_ cell .*" 1
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equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
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design -load postopt
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#select -assert-count 4 c:fd3 c:fd4 c:fd7 c:fd8
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select -assert-count 8 t:FD*
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logger -expect-no-warnings
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