mirror of https://github.com/YosysHQ/yosys.git
Supress error for unhandled \init if whole module selected
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@ -141,9 +141,10 @@ struct ZinitPass : public Pass {
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cell->setPort(ID::Q, initwire);
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}
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for (auto &it : initbits)
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if (donebits.count(it.first) == 0)
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log_error("Failed to handle init bit %s = %s.\n", log_signal(it.first), log_signal(it.second));
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if (!design->selected_whole_module(module))
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for (auto &it : initbits)
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if (donebits.count(it.first) == 0)
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log_error("Failed to handle init bit %s = %s.\n", log_signal(it.first), log_signal(it.second));
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}
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}
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} ZinitPass;
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