mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1633 from YosysHQ/eddie/fix_autoname
autoname: do not rename ports
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commit
61ffd2d199
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@ -56,7 +56,7 @@ int autoname_worker(Module *module)
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for (auto &conn : cell->connections()) {
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string suffix = stringf("_%s", log_id(conn.first));
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for (auto bit : conn.second)
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if (bit.wire != nullptr && bit.wire->name[0] == '$') {
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if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) {
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IdString new_name(cell->name.str() + suffix);
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int score = wire_score.at(bit.wire);
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if (cell->output(conn.first)) score = 0;
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@ -0,0 +1,19 @@
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read_ilang <<EOT
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autoidx 2
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module \top
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wire output 3 $y
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wire input 1 \a
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wire input 2 \b
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cell $and \b_$and_B
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \b
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connect \Y $y
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end
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end
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EOT
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autoname
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