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abc9_ops: -prep_holes -> -prep_xaiger, move padding to write_xaiger
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d21262ee04
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468386d67d
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@ -329,12 +329,11 @@ struct XAigerWriter
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}
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}
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// Fully pad all unused input connections of this box cell with S0
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// Fully pad all undriven output connections of this box cell with anonymous wires
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for (auto port_name : r.first->second) {
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auto w = box_module->wire(port_name);
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log_assert(w);
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auto rhs = cell->getPort(port_name);
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auto rhs = cell->connections_.at(port_name, SigSpec());
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rhs.append(Const(State::Sx, GetSize(w)-GetSize(rhs)));
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if (w->port_input)
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for (auto b : rhs) {
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SigBit I = sigmap(b);
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@ -429,6 +428,10 @@ struct XAigerWriter
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for (auto &bit : ci_bits) {
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aig_m++, aig_i++;
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// 1'bx may exist here due to a box output
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// that has been padded to its full width
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if (bit == State::Sx)
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continue;
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log_assert(!aig_map.count(bit));
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aig_map[bit] = 2*aig_m;
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}
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@ -244,9 +244,9 @@ struct Abc9Pass : public ScriptPass
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if (check_label("pre")) {
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run("scc -set_attr abc9_scc_id {}");
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if (help_mode)
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run("abc9_ops -mark_scc -prep_holes [-dff]", "(option for -dff)");
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run("abc9_ops -mark_scc -prep_xaiger [-dff]", "(option for -dff)");
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else
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run("abc9_ops -mark_scc -prep_holes" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
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run("abc9_ops -mark_scc -prep_xaiger" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
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run("select -set abc9_holes A:abc9_holes");
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run("flatten -wb @abc9_holes");
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run("techmap @abc9_holes");
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@ -143,7 +143,7 @@ void prep_dff(RTLIL::Module *module)
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}
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}
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void prep_holes(RTLIL::Module *module, bool dff)
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void prep_xaiger(RTLIL::Module *module, bool dff)
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{
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auto design = module->design;
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log_assert(design);
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@ -152,7 +152,7 @@ void prep_holes(RTLIL::Module *module, bool dff)
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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bool abc9_box_seen = false;
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dict<IdString, std::vector<IdString>> box_ports;
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for (auto cell : module->cells()) {
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if (cell->type == "$__ABC9_FF_")
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@ -165,7 +165,40 @@ void prep_holes(RTLIL::Module *module, bool dff)
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abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
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if (abc9_flop && !dff)
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continue;
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abc9_box_seen = abc9_box;
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auto r = box_ports.insert(cell->type);
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if (r.second) {
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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for (const auto &port_name : inst_module->ports) {
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auto w = inst_module->wire(port_name);
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log_assert(w);
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input) {
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if (carry_in != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(inst_module));
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carry_in = port_name;
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}
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if (w->port_output) {
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if (carry_out != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(inst_module));
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carry_out = port_name;
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}
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}
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else
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r.first->second.push_back(port_name);
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}
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if (carry_in != IdString() && carry_out == IdString())
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log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(inst_module));
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(inst_module));
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if (carry_in != IdString()) {
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r.first->second.push_back(carry_in);
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r.first->second.push_back(carry_out);
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}
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}
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}
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else if (!yosys_celltypes.cell_known(cell->type))
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continue;
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@ -183,7 +216,7 @@ void prep_holes(RTLIL::Module *module, bool dff)
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toposort.node(cell->name);
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}
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if (!abc9_box_seen)
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if (box_ports.empty())
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return;
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for (auto &it : bit_users)
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@ -211,7 +244,13 @@ void prep_holes(RTLIL::Module *module, bool dff)
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log_assert(no_loops);
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vector<Cell*> box_list;
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RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
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log_assert(holes_module);
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holes_module->set_bool_attribute("\\abc9_holes");
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dict<IdString, Cell*> cell_cache;
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int port_id = 1, box_count = 0;
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for (auto cell_name : toposort.sorted) {
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RTLIL::Cell *cell = module->cell(cell_name);
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log_assert(cell);
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@ -220,62 +259,10 @@ void prep_holes(RTLIL::Module *module, bool dff)
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if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
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continue;
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bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
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cell->attributes["\\abc9_box_seq"] = box_count++;
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// Fully pad all unused input connections of this box cell with S0
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// Fully pad all undriven output connections of this box cell with anonymous wires
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for (const auto &port_name : box_module->ports) {
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RTLIL::Wire* w = box_module->wire(port_name);
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log_assert(w);
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auto it = cell->connections_.find(port_name);
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if (w->port_input) {
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RTLIL::SigSpec rhs;
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if (it != cell->connections_.end()) {
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if (GetSize(it->second) < GetSize(w))
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it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
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rhs = it->second;
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}
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else {
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rhs = RTLIL::SigSpec(State::S0, GetSize(w));
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cell->setPort(port_name, rhs);
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}
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}
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if (w->port_output) {
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RTLIL::SigSpec rhs;
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auto it = cell->connections_.find(w->name);
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if (it != cell->connections_.end()) {
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if (GetSize(it->second) < GetSize(w))
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it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
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rhs = it->second;
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}
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else {
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Wire *wire = module->addWire(NEW_ID, GetSize(w));
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if (blackbox)
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wire->set_bool_attribute(ID(abc9_padding));
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rhs = wire;
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cell->setPort(port_name, rhs);
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}
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}
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}
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cell->attributes["\\abc9_box_seq"] = box_list.size();
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box_list.emplace_back(cell);
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}
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log_assert(!box_list.empty());
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RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
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log_assert(holes_module);
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holes_module->set_bool_attribute("\\abc9_holes");
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dict<IdString, Cell*> cell_cache;
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dict<IdString, std::vector<IdString>> box_ports;
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int port_id = 1;
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for (auto cell : box_list) {
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RTLIL::Module* orig_box_module = design->module(cell->type);
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log_assert(orig_box_module);
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IdString derived_name = orig_box_module->derive(design, cell->parameters);
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RTLIL::Module* box_module = design->module(derived_name);
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IdString derived_name = box_module->derive(design, cell->parameters);
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box_module = design->module(derived_name);
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auto r = cell_cache.insert(derived_name);
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auto &holes_cell = r.first->second;
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@ -283,40 +270,6 @@ void prep_holes(RTLIL::Module *module, bool dff)
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if (box_module->has_processes())
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Pass::call_on_module(design, box_module, "proc");
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auto r2 = box_ports.insert(cell->type);
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if (r2.second) {
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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for (const auto &port_name : box_module->ports) {
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auto w = box_module->wire(port_name);
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log_assert(w);
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input) {
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if (carry_in != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
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carry_in = port_name;
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}
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if (w->port_output) {
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if (carry_out != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
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carry_out = port_name;
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}
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}
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else
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r2.first->second.push_back(port_name);
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}
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if (carry_in != IdString() && carry_out == IdString())
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log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
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if (carry_in != IdString()) {
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r2.first->second.push_back(carry_in);
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r2.first->second.push_back(carry_out);
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}
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}
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if (box_module->get_bool_attribute("\\whitebox")) {
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holes_cell = holes_module->addCell(cell->name, derived_name);
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@ -770,6 +723,22 @@ struct Abc9OpsPass : public Pass {
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log("\n");
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log(" abc9_ops [options] [selection]\n");
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log("\n");
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log("This pass contains a set of supporting operations for use during ABC technology\n");
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log("mapping, and is expected to be called in conjunction with other operations from\n");
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log("the `abc9' script pass. Only fully-selected modules are supported.\n");
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log("\n");
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log(" -mark_scc\n");
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log(" for an arbitrarily chosen cell in each unique SCC of each selected module\n");
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log(" (tagged with an (* abc9_scc_id = <int> *) attribute), temporarily mark all\n");
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log(" wires driven by this cell's outputs with a (* keep *) attribute in order\n");
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log(" to break the SCC. this temporary attribute will be removed on -reintegrate.\n");
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log("\n");
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log(" -prep_xaiger\n");
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log(" prepare the design for XAIGER output. this includes computing the\n");
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log(" topological ordering of ABC9 boxes, as well as preparing the\n");
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log(" '<module-name>$holes' module that contains the logic behaviour of ABC9\n");
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log(" whiteboxes.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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@ -777,7 +746,7 @@ struct Abc9OpsPass : public Pass {
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bool mark_scc_mode = false;
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bool prep_dff_mode = false;
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bool prep_holes_mode = false;
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bool prep_xaiger_mode = false;
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bool reintegrate_mode = false;
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bool dff_mode = false;
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@ -792,8 +761,8 @@ struct Abc9OpsPass : public Pass {
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prep_dff_mode = true;
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continue;
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}
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if (arg == "-prep_holes") {
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prep_holes_mode = true;
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if (arg == "-prep_xaiger") {
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prep_xaiger_mode = true;
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continue;
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}
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if (arg == "-reintegrate") {
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@ -809,10 +778,10 @@ struct Abc9OpsPass : public Pass {
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extra_args(args, argidx, design);
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if (!(mark_scc_mode || prep_dff_mode || reintegrate_mode))
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log_cmd_error("At least one of -mark_scc, -prep_{dff,holes}, -reintegrate must be specified.\n");
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log_cmd_error("At least one of -mark_scc, -prep_{xaiger,dff}, -reintegrate must be specified.\n");
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if (dff_mode && !prep_holes_mode)
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log_cmd_error("'-dff' option is only relevant for -prep_holes.\n");
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if (dff_mode && !prep_xaiger_mode)
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log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n");
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for (auto mod : design->selected_modules()) {
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if (mod->get_bool_attribute("\\abc9_holes"))
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@ -830,8 +799,8 @@ struct Abc9OpsPass : public Pass {
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mark_scc(mod);
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if (prep_dff_mode)
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prep_dff(mod);
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if (prep_holes_mode)
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prep_holes(mod, dff_mode);
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if (prep_xaiger_mode)
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prep_xaiger(mod, dff_mode);
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if (reintegrate_mode)
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reintegrate(mod);
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}
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