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Fix CEA/CEB check

This commit is contained in:
Eddie Hung 2019-12-23 14:22:13 -08:00
parent edabe73377
commit 75acaff6f5
1 changed files with 2 additions and 2 deletions
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4
passes/pmgen/xilinx_dsp_cascade.pmg
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@ -257,7 +257,7 @@ code argQ clock AREG
else if (param(prev, \AREG, 2) == 2)
CEA = \CEA1;
else log_abort();
if (!dffcemux && port(prev, CEA, State::S0) != State::S0)
if (!dffcemux && port(prev, CEA, State::S0) != State::S1)
goto reject_AREG;
if (dffcemux && port(dffcemux, \S) != port(prev, CEA, State::S0))
goto reject_AREG;
@ -303,7 +303,7 @@ code argQ clock BREG
else log_abort();
}
else log_abort();
if (!dffcemux && port(prev, CEB, State::S0) != State::S0)
if (!dffcemux && port(prev, CEB, State::S0) != State::S1)
goto reject_BREG;
if (dffcemux && port(dffcemux, \S) != port(prev, CEB, State::S0))
goto reject_BREG;