mirror of https://github.com/YosysHQ/yosys.git
Use function arg
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0317a2b476
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@ -198,7 +198,7 @@ struct abc9_output_filter
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void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string script_file, std::string exe_file,
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vector<int> lut_costs, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
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const std::vector<RTLIL::Cell*> &/*cells*/, bool show_tempdir, std::string box_file, std::string lut_file,
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const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, std::string box_file, std::string lut_file,
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std::string wire_delay, const dict<int,IdString> &box_lookup, bool nomfs, std::string tempdir_name
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)
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{
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@ -359,7 +359,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
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dict<IdString, bool> abc9_box;
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vector<RTLIL::Cell*> boxes;
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for (auto cell : module->selected_cells()) {
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for (auto cell : cells) {
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if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_))) {
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module->remove(cell);
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continue;
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@ -960,18 +960,18 @@ struct Abc9MapPass : public Pass {
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}
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}
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for (auto module : design->selected_modules())
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for (auto mod : design->selected_modules())
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{
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if (module->processes.size() > 0)
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log_error("Module '%s' has processes!\n", log_id(module));
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if (mod->processes.size() > 0) {
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log("Skipping module %s as it contains processes.\n", log_id(mod));
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continue;
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}
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const std::vector<RTLIL::Cell*> all_cells = module->selected_cells();
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const std::vector<RTLIL::Cell*> all_cells = mod->selected_cells();
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design->selected_active_module = module->name.str();
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abc9_module(design, module, script_file, exe_file, lut_costs,
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abc9_module(design, mod, script_file, exe_file, lut_costs,
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delay_target, lutin_shared, fast_mode, all_cells, show_tempdir,
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box_file, lut_file, wire_delay, box_lookup, nomfs, tempdir_name);
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design->selected_active_module.clear();
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}
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log_pop();
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