mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
abc9: -dff improvements
This commit is contained in:
commit
69850204c4
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@ -85,7 +85,7 @@ struct XAigerWriter
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dict<SigBit, SigBit> not_map, alias_map;
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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vector<SigBit> ci_bits, co_bits;
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dict<SigBit, Cell*> ff_bits;
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vector<Cell*> ff_list;
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dict<SigBit, float> arrival_times;
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vector<pair<int, int>> aig_gates;
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@ -232,8 +232,7 @@ struct XAigerWriter
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unused_bits.erase(D);
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undriven_bits.erase(Q);
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alias_map[Q] = D;
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auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
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log_assert(r.second);
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ff_list.emplace_back(cell);
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continue;
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}
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@ -420,8 +419,7 @@ struct XAigerWriter
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aig_map[bit] = 2*aig_m;
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}
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for (const auto &i : ff_bits) {
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const Cell *cell = i.second;
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for (auto cell : ff_list) {
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const SigBit &q = sigmap(cell->getPort(ID::Q));
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aig_m++, aig_i++;
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log_assert(!aig_map.count(q));
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@ -468,8 +466,8 @@ struct XAigerWriter
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aig_outputs.push_back(aig);
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}
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for (auto &i : ff_bits) {
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const SigBit &d = i.first;
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for (auto cell : ff_list) {
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const SigBit &d = sigmap(cell->getPort(ID::D));
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aig_o++;
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aig_outputs.push_back(aig_map.at(d));
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}
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@ -541,16 +539,16 @@ struct XAigerWriter
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std::stringstream h_buffer;
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auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
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write_h_buffer(1);
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log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
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write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
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log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
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write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
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log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
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write_h_buffer(input_bits.size() + ff_bits.size());
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log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
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write_h_buffer(output_bits.size() + ff_bits.size());
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log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_list) + GetSize(ci_bits));
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write_h_buffer(GetSize(input_bits) + GetSize(ff_list) + GetSize(ci_bits));
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log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_list) + GetSize(co_bits));
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write_h_buffer(GetSize(output_bits) + GetSize(ff_list) + GetSize(co_bits));
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log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_list));
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write_h_buffer(GetSize(input_bits) + GetSize(ff_list));
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log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_list));
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write_h_buffer(GetSize(output_bits) + GetSize(ff_list));
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log_debug("boxNum = %d\n", GetSize(box_list));
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write_h_buffer(box_list.size());
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write_h_buffer(GetSize(box_list));
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auto write_buffer_float = [](std::stringstream &buffer, float f32) {
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buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
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@ -564,7 +562,7 @@ struct XAigerWriter
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//for (auto bit : output_bits)
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// write_o_buffer(0);
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if (!box_list.empty() || !ff_bits.empty()) {
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if (!box_list.empty() || !ff_list.empty()) {
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dict<IdString, std::tuple<int,int,int>> cell_cache;
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int box_count = 0;
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@ -601,17 +599,17 @@ struct XAigerWriter
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std::stringstream r_buffer;
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auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
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log_debug("flopNum = %d\n", GetSize(ff_bits));
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write_r_buffer(ff_bits.size());
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log_debug("flopNum = %d\n", GetSize(ff_list));
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write_r_buffer(ff_list.size());
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std::stringstream s_buffer;
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auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
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write_s_buffer(ff_bits.size());
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write_s_buffer(ff_list.size());
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dict<SigSpec, int> clk_to_mergeability;
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for (const auto &i : ff_bits) {
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const SigBit &d = i.first;
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const Cell *cell = i.second;
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for (const auto cell : ff_list) {
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const SigBit &d = sigmap(cell->getPort(ID::D));
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const SigBit &q = sigmap(cell->getPort(ID::Q));
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SigSpec clk_and_pol{sigmap(cell->getPort(ID::C)), cell->type[6] == 'P' ? State::S1 : State::S0};
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auto r = clk_to_mergeability.insert(std::make_pair(clk_and_pol, clk_to_mergeability.size()+1));
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@ -619,8 +617,7 @@ struct XAigerWriter
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log_assert(mergeability > 0);
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write_r_buffer(mergeability);
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SigBit Q = sigmap(cell->getPort(ID::Q));
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State init = init_map.at(Q, State::Sx);
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State init = init_map.at(q, State::Sx);
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log_debug("Cell '%s' (type %s) has (* init *) value '%s'.\n", log_id(cell), log_id(cell->type), log_signal(init));
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if (init == State::S1)
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write_s_buffer(1);
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@ -700,8 +697,6 @@ struct XAigerWriter
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for (auto wire : module->wires())
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{
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SigSpec sig = sigmap(wire);
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for (int i = 0; i < GetSize(wire); i++)
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{
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RTLIL::SigBit b(wire, i);
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@ -714,7 +709,6 @@ struct XAigerWriter
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if (output_bits.count(b)) {
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int o = ordered_outputs.at(b);
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output_lines[o] += stringf("output %d %d %s\n", o - GetSize(co_bits), wire->start_offset+i, log_id(wire));
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continue;
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}
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}
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}
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@ -775,7 +775,6 @@ void AigerReader::post_process()
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}
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}
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dict<int, Wire*> mergeability_to_clock;
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for (uint32_t i = 0; i < flopNum; i++) {
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RTLIL::Wire *d = outputs[outputs.size() - flopNum + i];
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log_assert(d);
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@ -895,7 +894,9 @@ void AigerReader::post_process()
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}
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else if (type == "box") {
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RTLIL::Cell* cell = module->cell(stringf("$box%d", variable));
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if (cell) // ABC could have optimised this box away
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if (!cell)
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log_debug("Box %d (%s) no longer exists.\n", variable, log_id(escaped_s));
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else
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module->rename(cell, escaped_s);
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}
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else
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@ -907,6 +908,8 @@ void AigerReader::post_process()
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auto name = wp.first;
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int min = wp.second.first;
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int max = wp.second.second;
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if (min == 0 && max == 0)
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continue;
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RTLIL::Wire *wire = module->wire(name);
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if (wire)
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@ -102,8 +102,6 @@ void check(RTLIL::Design *design, bool dff_mode)
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auto inst_module = design->module(cell->type);
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if (!inst_module)
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continue;
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if (!inst_module->get_blackbox_attribute())
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continue;
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IdString derived_type;
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Module *derived_module;
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if (cell->parameters.empty()) {
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@ -111,6 +109,10 @@ void check(RTLIL::Design *design, bool dff_mode)
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derived_module = inst_module;
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}
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else {
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// Check potential (since its value may depend on a parameter,
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// but not its existence)
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if (!inst_module->has_attribute(ID::abc9_flop))
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continue;
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derived_type = inst_module->derive(design, cell->parameters);
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derived_module = design->module(derived_type);
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log_assert(derived_module);
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@ -127,20 +129,20 @@ void check(RTLIL::Design *design, bool dff_mode)
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for (auto derived_cell : derived_module->cells()) {
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if (derived_cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_))) {
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if (found)
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log_error("Module '%s' with (* abc9_flop *) contains more than one $_DFF_[NP]_ cell.\n", log_id(derived_module));
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log_error("Whitebox '%s' with (* abc9_flop *) contains more than one $_DFF_[NP]_ cell.\n", log_id(derived_module));
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found = true;
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SigBit Q = derived_cell->getPort(ID::Q);
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log_assert(GetSize(Q.wire) == 1);
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if (!Q.wire->port_output)
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log_error("Module '%s' contains a %s cell where its 'Q' port does not drive a module output!\n", log_id(derived_module), log_id(derived_cell->type));
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log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell where its 'Q' port does not drive a module output.\n", log_id(derived_module), log_id(derived_cell->type));
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Const init = Q.wire->attributes.at(ID::init, State::Sx);
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log_assert(GetSize(init) == 1);
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}
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else if (unsupported.count(derived_cell->type))
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log_error("Module '%s' with (* abc9_flop *) contains a %s cell, which is not supported for sequential synthesis.\n", log_id(derived_module), log_id(derived_cell->type));
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log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell, which is not supported for sequential synthesis.\n", log_id(derived_module), log_id(derived_cell->type));
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}
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}
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}
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@ -173,8 +175,6 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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auto inst_module = design->module(cell->type);
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if (!inst_module)
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continue;
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if (!inst_module->get_blackbox_attribute())
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continue;
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IdString derived_type;
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Module *derived_module;
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if (cell->parameters.empty()) {
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@ -182,6 +182,10 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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derived_module = inst_module;
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}
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else {
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// Check potential for any one of those three
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// (since its value may depend on a parameter, but not its existence)
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if (!inst_module->has_attribute(ID::abc9_flop) && !inst_module->has_attribute(ID::abc9_box) && !inst_module->get_bool_attribute(ID::abc9_bypass))
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continue;
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derived_type = inst_module->derive(design, cell->parameters);
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derived_module = design->module(derived_type);
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}
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@ -211,7 +215,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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// Block sequential synthesis on cells with (* init *) != 1'b0
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// because ABC9 doesn't support them
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if (init != State::S0) {
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log_warning("Module '%s' contains a %s cell with non-zero initial state -- this is not unsupported for ABC9 sequential synthesis. Treating as a blackbox.\n", log_id(derived_module), log_id(derived_cell->type));
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log_warning("Whitebox '%s' with (* abc9_flop *) contains a %s cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.\n", log_id(derived_module), log_id(derived_cell->type));
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derived_module->set_bool_attribute(ID::abc9_flop, false);
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}
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break;
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@ -232,10 +236,8 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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auto w = unmap_module->addWire(port, derived_module->wire(port));
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// Do not propagate (* init *) values into the box,
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// in fact, remove it from outside too
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if (w->port_output && w->attributes.erase(ID::init)) {
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auto r = unmap_module->addWire(stringf("\\_TECHMAP_REMOVEINIT_%s_", log_id(port)));
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unmap_module->connect(r, State::S1);
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}
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if (w->port_output)
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w->attributes.erase(ID::init);
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}
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unmap_module->ports = derived_module->ports;
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unmap_module->check();
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@ -1112,7 +1114,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
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for (auto w : mapped_mod->wires()) {
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auto nw = module->addWire(remap_name(w->name), GetSize(w));
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nw->start_offset = w->start_offset;
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// Remove all (* init *) since they only existon $_DFF_[NP]_
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// Remove all (* init *) since they only exist on $_DFF_[NP]_
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w->attributes.erase(ID::init);
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}
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@ -1149,16 +1151,36 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
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}
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}
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SigMap initmap;
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if (dff_mode) {
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// Build a sigmap prioritising bits with (* init *)
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initmap.set(module);
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for (auto w : module->wires()) {
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auto it = w->attributes.find(ID::init);
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if (it == w->attributes.end())
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continue;
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for (auto i = 0; i < GetSize(w); i++)
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if (it->second[i] == State::S0 || it->second[i] == State::S1)
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initmap.add(w);
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}
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}
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std::vector<Cell*> boxes;
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for (auto cell : module->cells().to_vector()) {
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if (cell->has_keep_attr())
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continue;
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// Short out $_DFF_[NP]_ cells since the flop box already has
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// all the information we need to reconstruct cell
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// Short out (so that existing name can be preserved) and remove
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// $_DFF_[NP]_ cells since flop box already has all the information
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// we need to reconstruct them
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if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep)) {
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module->connect(cell->getPort(ID::Q), cell->getPort(ID::D));
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SigBit Q = cell->getPort(ID::Q);
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module->connect(Q, cell->getPort(ID::D));
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module->remove(cell);
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auto Qi = initmap(Q);
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auto it = Qi.wire->attributes.find(ID::init);
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if (it != Qi.wire->attributes.end())
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it->second[Qi.offset] = State::Sx;
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}
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else if (cell->type.in(ID($_AND_), ID($_NOT_)))
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module->remove(cell);
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@ -1301,7 +1323,25 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
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mapped_cell->connections_.erase(jt);
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auto abc9_flop = box_module->get_bool_attribute(ID::abc9_flop);
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if (!abc9_flop) {
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if (abc9_flop) {
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// Link this sole flop box output to the output of the existing
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// flop box, so that any (public) signal it drives will be
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// preserved
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SigBit old_q;
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for (const auto &port_name : box_ports.at(existing_cell->type)) {
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RTLIL::Wire *w = box_module->wire(port_name);
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log_assert(w);
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if (!w->port_output)
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continue;
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log_assert(old_q == SigBit());
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log_assert(GetSize(w) == 1);
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old_q = existing_cell->getPort(port_name);
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}
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auto new_q = outputs[0];
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new_q.wire = module->wires_.at(remap_name(new_q.wire->name));
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module->connect(old_q, new_q);
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}
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else {
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for (const auto &i : inputs)
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bit_users[i].insert(mapped_cell->name);
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for (const auto &i : outputs)
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@ -1334,11 +1374,12 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
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c.wire = module->wires_.at(remap_name(c.wire->name));
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newsig.append(c);
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}
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cell->setPort(port_name, newsig);
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if (w->port_input && !abc9_flop)
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for (const auto &i : newsig)
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bit2sinks[i].push_back(cell);
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cell->setPort(port_name, std::move(newsig));
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}
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}
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@ -1400,7 +1441,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
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// treated as being "free"), in particular driving primary
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// outputs (real primary outputs, or cells treated as blackboxes)
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// or driving box inputs.
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// Instead of just mapping those $_NOT_ gates into 2-input $lut-s
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// Instead of just mapping those $_NOT_ gates into 1-input $lut-s
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// at an area and delay cost, see if it is possible to push
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// this $_NOT_ into the driving LUT, or into all sink LUTs.
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// When this is not possible, (i.e. this signal drives two primary
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@ -1,5 +1,5 @@
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(* techmap_celltype = "$__DFF_N__$abc9_flop $__DFF_P__$abc9_flop" *)
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module $__DFF_x__$abc9_flop (input C, D, Q, output n1);
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module $__DFF_x__$abc9_flop (input C, D, (* init = 1'b0 *) input Q, output n1);
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parameter _TECHMAP_CELLTYPE_ = "";
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generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N__$abc9_flop")
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$_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
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@ -50,10 +50,10 @@ FDCE_1 /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
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FDPE_1 #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
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endmodule
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EOT
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logger -expect warning "Module '\$paramod\\FDRE\\INIT=1' contains a \$dff cell .*" 1
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logger -expect warning "Module '\$paramod\\FDRE_1\\INIT=1' contains a \$dff cell .*" 1
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logger -expect warning "Module 'FDSE' contains a \$dff cell .*" 1
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logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$dff cell .*" 1
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logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
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logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
|
||||
logger -expect warning "Whitebox 'FDSE' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
|
||||
logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
|
||||
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
|
||||
design -load postopt
|
||||
select -assert-count 8 t:FD*
|
||||
|
@ -82,4 +82,53 @@ select -assert-count 1 t:FDPE
|
|||
select -assert-count 2 t:INV
|
||||
select -assert-count 0 t:FD* t:INV %% t:* %D
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module top(input clk, input d, output q);
|
||||
reg r;
|
||||
always @(posedge clk) begin
|
||||
r <= d;
|
||||
end
|
||||
assign q = ~r;
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
|
||||
design -load postopt
|
||||
select -assert-count 1 t:FDRE %co w:r %i
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module top(input clk, input a, b, output reg q1, output q2);
|
||||
reg r;
|
||||
always @(posedge clk) begin
|
||||
q1 <= a | b;
|
||||
r <= ~(~a & ~b);
|
||||
end
|
||||
assign q2 = r;
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
|
||||
design -load postopt
|
||||
select -assert-count 1 t:FDRE %co %a w:r %i
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module top(input clk, input a, b, output o);
|
||||
reg r1, r2;
|
||||
always @(posedge clk) begin
|
||||
r1 <= a | b;
|
||||
r2 <= ~(~a & ~b);
|
||||
end
|
||||
assign o = r1 | r2;
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
|
||||
|
||||
|
||||
logger -expect-no-warnings
|
||||
|
|
|
@ -97,4 +97,5 @@ select -assert-count 3 t:$_DFF_N_
|
|||
select -assert-none c:ff1 c:ff2 c:ff4 %% c:* %D
|
||||
clean
|
||||
select -assert-count 2 a:init
|
||||
select -assert-none w:w w:z %% a:init %D
|
||||
select -assert-count 1 w:w a:init %i
|
||||
select -assert-count 1 c:ff4 %co c:ff4 %d %a a:init %i
|
||||
|
|
Loading…
Reference in New Issue