riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it

This commit is contained in:
Eddie Hung 2020-05-14 00:29:45 -07:00
parent fa31e84112
commit 13f9d65b6f
4 changed files with 13 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
passes/techmap/abc9_ops.cc
View File

@ -1101,17 +1101,6 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
map_autoidx = autoidx++;
// TODO: Get rid of this expensive lookup
dict<SigBit,vector<SigBit>> sig2inits;
SigMap sigmap(module);
for (auto w : module->wires()) {
auto it = w->attributes.find(ID::init);
if (it == w->attributes.end())
continue;
for (const auto &b : SigSpec(w))
sig2inits[sigmap(b)].emplace_back(b);
}
RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name.c_str()));
if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
@ -1164,12 +1153,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// Short out $_DFF_[NP]_ cells since the flop box already has
// all the information we need to reconstruct cell
if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
SigBit Q = cell->getPort(ID::Q);
auto it = sig2inits.find(Q);
if (it != sig2inits.end())
for (const auto &b : it->second)
b.wire->attributes.at(ID::init)[b.offset] = State::Sx;
module->connect(Q, cell->getPort(ID::D));
module->connect(cell->getPort(ID::Q), cell->getPort(ID::D));
module->remove(cell);
}
else if (cell->type.in(ID($_AND_), ID($_NOT_)))

4
techlibs/common/abc9_map.v
View File

@ -3,14 +3,14 @@
module $_DFF_x_(input C, D, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
parameter _TECHMAP_CELLTYPE_ = "";
(* init=_TECHMAP_WIREINIT_Q_ *) wire D_;
wire D_;
generate if (_TECHMAP_CELLTYPE_ == "$_DFF_N_") begin
if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin
$__DFF_N__$abc9_flop _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
$_DFF_N_ ff (.C(C), .D(D_), .Q(Q));
end
else
$__DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));// hide from abc9 using $__ prefix
$__DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); // hide from abc9 using $__ prefix
end
else if (_TECHMAP_CELLTYPE_ == "$_DFF_P_") begin
if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin

5
techlibs/common/abc9_unmap.v
View File

@ -1,6 +1,5 @@
(* techmap_celltype = "$__DFF_N__$abc9_flop $__DFF_P__$abc9_flop" *)
module $__DFF_x__$abc9_flop (input C, D, Q, (* init = INIT *) output n1);
parameter [0:0] INIT = 1'bx;
module $__DFF_x__$abc9_flop (input C, D, Q, output n1);
parameter _TECHMAP_CELLTYPE_ = "";
generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N__$abc9_flop")
$_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
@ -12,7 +11,7 @@ module $__DFF_x__$abc9_flop (input C, D, Q, (* init = INIT *) output n1);
endmodule
(* techmap_celltype = "$__DFF_N_ $__DFF_P_" *)
module $__DFF_N__$abc9_flop (input C, D, output Q);
module $__DFF_x_ (input C, D, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N_")
$_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));

11
tests/various/abc9.ys
View File

@ -78,18 +78,23 @@ abc9
design -reset
read_verilog -icells <<EOT
module abc9_test038(input clk, output w, x, y);
module abc9_test038(input clk, output w, x, y, z);
(* init=1'b1 *) wire w;
$_DFF_N_ ff1(.C(clk), .D(1'b1), .Q(w));
(* init=1'bx *) wire x;
$_DFF_N_ ff2(.C(clk), .D(1'b0), .Q(x));
(* init=1'b0 *) wire y;
$_DFF_N_ ff3(.C(clk), .D(1'b0), .Q(y));
(* init=1'b0 *) wire z;
$_DFF_N_ ff4(.C(clk), .D(1'b1), .Q(z));
endmodule
EOT
simplemap
equiv_opt abc9 -lut 4 -dff
design -load postopt
cd abc9_test038
select -assert-count 2 t:$_DFF_N_
select -assert-none c:ff1 c:ff2 %% c:* %D
select -assert-count 3 t:$_DFF_N_
select -assert-none c:ff1 c:ff2 c:ff4 %% c:* %D
clean
select -assert-count 2 a:init
select -assert-none w:w w:z %% a:init %D