mirror of https://github.com/YosysHQ/yosys.git
parent
22ef5701c0
commit
2d3753d730
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@ -229,11 +229,13 @@ struct IopadmapPass : public Pass {
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for (auto module : design->selected_modules())
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{
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dict<Wire *, dict<int, pair<Cell *, IdString>>> rewrite_bits;
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pool<SigSig> remove_conns;
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if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
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{
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dict<SigBit, Cell *> tbuf_bits;
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pool<SigBit> driven_bits;
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dict<SigBit, SigSig> z_conns;
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// Gather tristate buffers and always-on drivers.
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for (auto cell : module->cells())
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@ -252,8 +254,10 @@ struct IopadmapPass : public Pass {
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for (int i = 0; i < GetSize(conn.first); i++) {
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SigBit dstbit = conn.first[i];
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SigBit srcbit = conn.second[i];
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if (!srcbit.wire && srcbit.data == State::Sz)
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if (!srcbit.wire && srcbit.data == State::Sz) {
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z_conns[dstbit] = conn;
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continue;
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}
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driven_bits.insert(dstbit);
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}
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@ -302,6 +306,8 @@ struct IopadmapPass : public Pass {
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// enable.
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en_sig = SigBit(State::S0);
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data_sig = SigBit(State::Sx);
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if (z_conns.count(wire_bit))
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remove_conns.insert(z_conns[wire_bit]);
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}
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if (wire->port_input)
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@ -454,6 +460,14 @@ struct IopadmapPass : public Pass {
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}
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}
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if (!remove_conns.empty()) {
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std::vector<SigSig> new_conns;
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for (auto &conn : module->connections())
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if (!remove_conns.count(conn))
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new_conns.push_back(conn);
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module->new_connections(new_conns);
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}
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for (auto &it : rewrite_bits) {
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RTLIL::Wire *wire = it.first;
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RTLIL::Wire *new_wire = module->addWire(
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@ -55,13 +55,19 @@ obuf b (.i(i), .o(tmp));
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assign o = tmp;
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endmodule
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module k(inout o, o2);
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assign o = 1'bz;
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endmodule
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EOT
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opt_clean
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tribuf
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simplemap
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iopadmap -bits -inpad ibuf o:i -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io a b c d e f g h i j
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iopadmap -bits -inpad ibuf o:i -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io a b c d e f g h i j k
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opt_clean
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hierarchy -check
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check
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select -assert-count 1 a/t:ibuf
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select -assert-count 1 a/t:obuf
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@ -140,6 +146,8 @@ select -assert-count 0 i/t:obuf
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select -assert-count 1 j/t:ibuf
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select -assert-count 1 j/t:obuf
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select -assert-count 2 k/t:iobuf
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# Check that \init attributes get moved from output buffer
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# to buffer input
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