mirror of https://github.com/YosysHQ/yosys.git
Add abc9_ops -prep_holes
This commit is contained in:
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16c4ec7eda
commit
b50de28c04
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@ -680,12 +680,11 @@ struct XAigerWriter
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// write_o_buffer(0);
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if (!box_list.empty() || !ff_bits.empty()) {
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RTLIL::Module *holes_module = module->design->addModule("$__holes__");
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RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
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log_assert(holes_module);
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dict<IdString, Cell*> cell_cache;
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int port_id = 1;
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int box_count = 0;
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for (auto cell : box_list) {
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RTLIL::Module* orig_box_module = module->design->module(cell->type);
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@ -696,85 +695,21 @@ struct XAigerWriter
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Pass::call_on_module(module->design, box_module, "proc");
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int box_inputs = 0, box_outputs = 0;
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auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
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Cell *holes_cell = r.first->second;
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if (r.second && box_module->get_bool_attribute("\\whitebox")) {
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holes_cell = holes_module->addCell(cell->name, cell->type);
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holes_cell->parameters = cell->parameters;
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r.first->second = holes_cell;
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// Since Module::derive() will create a new module, there
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// is a chance that the ports will be alphabetically ordered
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// again, which is a problem when carry-chains are involved.
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// Inherit the port ordering from the original module here...
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// (and set the port_id below, when iterating through those)
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log_assert(GetSize(box_module->ports) == GetSize(orig_box_module->ports));
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box_module->ports = orig_box_module->ports;
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}
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// NB: Assume box_module->ports are sorted alphabetically
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// (as RTLIL::Module::fixup_ports() would do)
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int box_port_id = 1;
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for (const auto &port_name : box_module->ports) {
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RTLIL::Wire *w = box_module->wire(port_name);
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log_assert(w);
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if (r.second)
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w->port_id = box_port_id++;
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RTLIL::Wire *holes_wire;
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RTLIL::SigSpec port_sig;
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if (w->port_input)
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for (int i = 0; i < GetSize(w); i++) {
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box_inputs++;
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holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
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if (!holes_wire) {
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holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
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holes_wire->port_input = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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}
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if (holes_cell)
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port_sig.append(holes_wire);
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}
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if (w->port_output) {
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box_inputs += GetSize(w);
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if (w->port_output)
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box_outputs += GetSize(w);
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for (int i = 0; i < GetSize(w); i++) {
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if (GetSize(w) == 1)
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holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
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else
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holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
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holes_wire->port_output = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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if (holes_cell)
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port_sig.append(holes_wire);
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else
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holes_module->connect(holes_wire, State::S0);
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}
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}
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if (!port_sig.empty()) {
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if (r.second)
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holes_cell->setPort(w->name, port_sig);
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else
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holes_module->connect(holes_cell->getPort(w->name), port_sig);
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}
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}
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// For flops only, create an extra 1-bit input that drives a new wire
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// called "<cell>.$abc9_currQ" that is used below
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if (box_module->get_bool_attribute("\\abc9_flop")) {
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log_assert(holes_cell);
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if (box_module->get_bool_attribute("\\abc9_flop"))
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box_inputs++;
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Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
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if (!holes_wire) {
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holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
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holes_wire->port_input = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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}
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Wire *w = holes_module->addWire(stringf("%s.$abc9_currQ", cell->name.c_str()));
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holes_module->connect(w, holes_wire);
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}
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write_h_buffer(box_inputs);
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write_h_buffer(box_outputs);
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@ -815,79 +750,20 @@ struct XAigerWriter
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f.write(buffer_str.data(), buffer_str.size());
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if (holes_module) {
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log_push();
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// NB: fixup_ports() will sort ports by name
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//holes_module->fixup_ports();
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holes_module->check();
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// Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
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// since boxes may contain parameters in which case `flatten` would have
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// created a new $paramod ...
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Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap");
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dict<SigSig, SigSig> replace;
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for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
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auto cell = it->second;
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if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
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"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
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SigBit D = cell->getPort("\\D");
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SigBit Q = cell->getPort("\\Q");
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// Remove the DFF cell from what needs to be a combinatorial box
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it = holes_module->cells_.erase(it);
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Wire *port;
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if (GetSize(Q.wire) == 1)
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port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
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else
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port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
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log_assert(port);
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// Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
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// in order to extract the combinatorial control logic that feeds the box
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// (i.e. clock enable, synchronous reset, etc.)
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replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
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// Since `flatten` above would have created wires named "<cell>.Q",
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// extract the pre-techmap cell name
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auto pos = Q.wire->name.str().rfind(".");
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log_assert(pos != std::string::npos);
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IdString driver = Q.wire->name.substr(0, pos);
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// And drive the signal that was previously driven by "DFF.Q" (typically
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// used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
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// wire (which itself is driven an input port) we inserted above
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Wire *currQ = holes_module->wire(stringf("%s.$abc9_currQ", driver.c_str()));
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log_assert(currQ);
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holes_module->connect(Q, currQ);
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continue;
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}
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else if (!cell->type.in("$_NOT_", "$_AND_"))
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log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
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++it;
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}
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for (auto &conn : holes_module->connections_) {
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auto it = replace.find(conn);
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if (it != replace.end())
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conn = it->second;
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}
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// Move into a new (temporary) design so that "clean" will only
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// operate (and run checks on) this one module
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RTLIL::Design *holes_design = new RTLIL::Design;
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module->design->modules_.erase(holes_module->name);
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holes_design->add(holes_module);
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Pass::call(holes_design, "opt -purge");
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module->design->selection_stack.emplace_back(false);
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module->design->selection().select(holes_module);
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std::stringstream a_buffer;
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XAigerWriter writer(holes_module, true /* holes_mode */);
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writer.write_aiger(a_buffer, false /*ascii_mode*/);
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delete holes_design;
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module->design->selection_stack.pop_back();
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f << "a";
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std::string buffer_str = a_buffer.str();
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int32_t buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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log_pop();
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}
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}
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@ -207,7 +207,7 @@ struct Abc9Pass : public ScriptPass
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tempdir_name = make_temp_dir(tempdir_name);
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run("scc -set_attr abc9_scc_id {}");
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run("abc9_ops -break_scc -prep_dff");
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run("abc9_ops -break_scc -prep_dff -prep_holes");
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run("aigmap");
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run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()),
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"write_xaiger -map <abc-temp-dir>/input.sym <abc-temp-dir>/input.xaig");
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@ -20,6 +20,7 @@
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/utils.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -75,7 +76,8 @@ void break_scc(RTLIL::Module *module)
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module->fixup_ports();
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}
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void unbreak_scc(RTLIL::Module *module) {
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void unbreak_scc(RTLIL::Module *module)
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{
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// Now 'unexpose' those wires by undoing
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// the expose operation -- remove them from PO/PI
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// and re-connecting them back together
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@ -96,7 +98,8 @@ void unbreak_scc(RTLIL::Module *module) {
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module->fixup_ports();
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}
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void prep_dff(RTLIL::Module *module) {
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void prep_dff(RTLIL::Module *module)
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{
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auto design = module->design;
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log_assert(design);
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@ -134,6 +137,306 @@ void prep_dff(RTLIL::Module *module) {
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}
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}
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void prep_holes(RTLIL::Module *module)
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{
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auto design = module->design;
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log_assert(design);
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SigMap sigmap(module);
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// TODO: Speed up toposort -- ultimately we care about
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// box ordering, but not individual AIG cells
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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bool abc9_box_seen = false;
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for (auto cell : module->selected_cells()) {
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if (cell->type == "$_NOT_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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toposort.node(cell->name);
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bit_users[A].insert(cell->name);
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bit_drivers[Y].insert(cell->name);
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continue;
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}
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if (cell->type == "$_AND_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit B = sigmap(cell->getPort("\\B").as_bit());
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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toposort.node(cell->name);
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bit_users[A].insert(cell->name);
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bit_users[B].insert(cell->name);
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bit_drivers[Y].insert(cell->name);
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continue;
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}
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if (cell->type == "$__ABC9_FF_")
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continue;
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RTLIL::Module* inst_module = design->module(cell->type);
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if (inst_module) {
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if (!inst_module->attributes.count("\\abc9_box_id") || cell->get_bool_attribute("\\abc9_keep"))
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continue;
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for (const auto &conn : cell->connections()) {
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auto port_wire = inst_module->wire(conn.first);
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// Ignore inout for the sake of topographical ordering
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if (port_wire->port_input && !port_wire->port_output)
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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if (port_wire->port_output)
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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}
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abc9_box_seen = true;
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toposort.node(cell->name);
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}
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}
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if (!abc9_box_seen)
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return;
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for (auto &it : bit_users)
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if (bit_drivers.count(it.first))
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for (auto driver_cell : bit_drivers.at(it.first))
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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#if 0
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toposort.analyze_loops = true;
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#endif
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bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
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#if 0
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unsigned i = 0;
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for (auto &it : toposort.loops) {
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log(" loop %d\n", i++);
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for (auto cell_name : it) {
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auto cell = module->cell(cell_name);
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log_assert(cell);
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log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
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}
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}
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#endif
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log_assert(no_loops);
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vector<Cell*> box_list;
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for (auto cell_name : toposort.sorted) {
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RTLIL::Cell *cell = module->cell(cell_name);
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log_assert(cell);
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RTLIL::Module* box_module = design->module(cell->type);
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if (!box_module || !box_module->attributes.count("\\abc9_box_id")
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|| cell->get_bool_attribute("\\abc9_keep"))
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continue;
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bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
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// Fully pad all unused input connections of this box cell with S0
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// Fully pad all undriven output connections of this box cell with anonymous wires
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// NB: Assume box_module->ports are sorted alphabetically
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// (as RTLIL::Module::fixup_ports() would do)
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for (const auto &port_name : box_module->ports) {
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RTLIL::Wire* w = box_module->wire(port_name);
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log_assert(w);
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auto it = cell->connections_.find(port_name);
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if (w->port_input) {
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RTLIL::SigSpec rhs;
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if (it != cell->connections_.end()) {
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if (GetSize(it->second) < GetSize(w))
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it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
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rhs = it->second;
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}
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else {
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rhs = RTLIL::SigSpec(State::S0, GetSize(w));
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cell->setPort(port_name, rhs);
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}
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}
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if (w->port_output) {
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RTLIL::SigSpec rhs;
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auto it = cell->connections_.find(w->name);
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if (it != cell->connections_.end()) {
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if (GetSize(it->second) < GetSize(w))
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it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
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rhs = it->second;
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}
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else {
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Wire *wire = module->addWire(NEW_ID, GetSize(w));
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if (blackbox)
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wire->set_bool_attribute(ID(abc9_padding));
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rhs = wire;
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cell->setPort(port_name, rhs);
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}
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}
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}
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box_list.emplace_back(cell);
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}
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log_assert(!box_list.empty());
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RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
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log_assert(holes_module);
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dict<IdString, Cell*> cell_cache;
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int port_id = 1;
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for (auto cell : box_list) {
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RTLIL::Module* orig_box_module = design->module(cell->type);
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log_assert(orig_box_module);
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IdString derived_name = orig_box_module->derive(design, cell->parameters);
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RTLIL::Module* box_module = design->module(derived_name);
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if (box_module->has_processes())
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Pass::call_on_module(design, box_module, "proc");
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int box_inputs = 0;
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auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
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Cell *holes_cell = r.first->second;
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if (r.second && box_module->get_bool_attribute("\\whitebox")) {
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holes_cell = holes_module->addCell(cell->name, cell->type);
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holes_cell->parameters = cell->parameters;
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r.first->second = holes_cell;
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// Since Module::derive() will create a new module, there
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// is a chance that the ports will be alphabetically ordered
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// again, which is a problem when carry-chains are involved.
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// Inherit the port ordering from the original module here...
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// (and set the port_id below, when iterating through those)
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log_assert(GetSize(box_module->ports) == GetSize(orig_box_module->ports));
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box_module->ports = orig_box_module->ports;
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}
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// NB: Assume box_module->ports are sorted alphabetically
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// (as RTLIL::Module::fixup_ports() would do)
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int box_port_id = 1;
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for (const auto &port_name : box_module->ports) {
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RTLIL::Wire *w = box_module->wire(port_name);
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log_assert(w);
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if (r.second)
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w->port_id = box_port_id++;
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RTLIL::Wire *holes_wire;
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RTLIL::SigSpec port_sig;
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if (w->port_input)
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for (int i = 0; i < GetSize(w); i++) {
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box_inputs++;
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holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
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if (!holes_wire) {
|
||||
holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
|
||||
holes_wire->port_input = true;
|
||||
holes_wire->port_id = port_id++;
|
||||
holes_module->ports.push_back(holes_wire->name);
|
||||
}
|
||||
if (holes_cell)
|
||||
port_sig.append(holes_wire);
|
||||
}
|
||||
if (w->port_output)
|
||||
for (int i = 0; i < GetSize(w); i++) {
|
||||
if (GetSize(w) == 1)
|
||||
holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
|
||||
else
|
||||
holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
|
||||
holes_wire->port_output = true;
|
||||
holes_wire->port_id = port_id++;
|
||||
holes_module->ports.push_back(holes_wire->name);
|
||||
if (holes_cell)
|
||||
port_sig.append(holes_wire);
|
||||
else
|
||||
holes_module->connect(holes_wire, State::S0);
|
||||
}
|
||||
if (!port_sig.empty()) {
|
||||
if (r.second)
|
||||
holes_cell->setPort(w->name, port_sig);
|
||||
else
|
||||
holes_module->connect(holes_cell->getPort(w->name), port_sig);
|
||||
}
|
||||
}
|
||||
|
||||
// For flops only, create an extra 1-bit input that drives a new wire
|
||||
// called "<cell>.$abc9_currQ" that is used below
|
||||
if (box_module->get_bool_attribute("\\abc9_flop")) {
|
||||
log_assert(holes_cell);
|
||||
|
||||
box_inputs++;
|
||||
Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
|
||||
if (!holes_wire) {
|
||||
holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
|
||||
holes_wire->port_input = true;
|
||||
holes_wire->port_id = port_id++;
|
||||
holes_module->ports.push_back(holes_wire->name);
|
||||
}
|
||||
Wire *w = holes_module->addWire(stringf("%s.$abc9_currQ", cell->name.c_str()));
|
||||
holes_module->connect(w, holes_wire);
|
||||
}
|
||||
}
|
||||
|
||||
log_push();
|
||||
|
||||
// NB: fixup_ports() will sort ports by name
|
||||
//holes_module->fixup_ports();
|
||||
holes_module->check();
|
||||
|
||||
// Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
|
||||
// since boxes may contain parameters in which case `flatten` would have
|
||||
// created a new $paramod ...
|
||||
Pass::call_on_module(design, holes_module, "flatten -wb; techmap; aigmap");
|
||||
|
||||
dict<SigSig, SigSig> replace;
|
||||
for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
|
||||
auto cell = it->second;
|
||||
if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
|
||||
"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
|
||||
SigBit D = cell->getPort("\\D");
|
||||
SigBit Q = cell->getPort("\\Q");
|
||||
// Remove the DFF cell from what needs to be a combinatorial box
|
||||
it = holes_module->cells_.erase(it);
|
||||
Wire *port;
|
||||
if (GetSize(Q.wire) == 1)
|
||||
port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
|
||||
else
|
||||
port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
|
||||
log_assert(port);
|
||||
// Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
|
||||
// in order to extract the combinatorial control logic that feeds the box
|
||||
// (i.e. clock enable, synchronous reset, etc.)
|
||||
replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
|
||||
// Since `flatten` above would have created wires named "<cell>.Q",
|
||||
// extract the pre-techmap cell name
|
||||
auto pos = Q.wire->name.str().rfind(".");
|
||||
log_assert(pos != std::string::npos);
|
||||
IdString driver = Q.wire->name.substr(0, pos);
|
||||
// And drive the signal that was previously driven by "DFF.Q" (typically
|
||||
// used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
|
||||
// wire (which itself is driven an input port) we inserted above
|
||||
Wire *currQ = holes_module->wire(stringf("%s.$abc9_currQ", driver.c_str()));
|
||||
log_assert(currQ);
|
||||
holes_module->connect(Q, currQ);
|
||||
continue;
|
||||
}
|
||||
else if (!cell->type.in("$_NOT_", "$_AND_"))
|
||||
log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
|
||||
++it;
|
||||
}
|
||||
|
||||
for (auto &conn : holes_module->connections_) {
|
||||
auto it = replace.find(conn);
|
||||
if (it != replace.end())
|
||||
conn = it->second;
|
||||
}
|
||||
|
||||
// Move into a new (temporary) design so that "clean" will only
|
||||
// operate (and run checks on) this one module
|
||||
RTLIL::Design *holes_design = new RTLIL::Design;
|
||||
holes_design->add(holes_module);
|
||||
Pass::call(holes_design, "opt -purge");
|
||||
holes_design->modules_.erase(holes_module->name);
|
||||
holes_module->design = design;
|
||||
|
||||
log_pop();
|
||||
}
|
||||
|
||||
struct Abc9PrepPass : public Pass {
|
||||
Abc9PrepPass() : Pass("abc9_ops", "helper functions for ABC9") { }
|
||||
void help() YS_OVERRIDE
|
||||
|
@ -151,6 +454,7 @@ struct Abc9PrepPass : public Pass {
|
|||
bool break_scc_mode = false;
|
||||
bool unbreak_scc_mode = false;
|
||||
bool prep_dff_mode = false;
|
||||
bool prep_holes_mode = false;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
|
@ -167,6 +471,10 @@ struct Abc9PrepPass : public Pass {
|
|||
prep_dff_mode = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-prep_holes") {
|
||||
prep_holes_mode = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
@ -178,6 +486,8 @@ struct Abc9PrepPass : public Pass {
|
|||
unbreak_scc(mod);
|
||||
if (prep_dff_mode)
|
||||
prep_dff(mod);
|
||||
if (prep_holes_mode)
|
||||
prep_holes(mod);
|
||||
}
|
||||
}
|
||||
} Abc9PrepPass;
|
||||
|
|
Loading…
Reference in New Issue