riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Clean up `passes/cmds/connwrappers.cc`.

This commit is contained in:
Alberto Gonzalez 2020-04-06 06:08:11 +00:00
parent d61a6b81fc
commit 968230261f
No known key found for this signature in database
GPG Key ID: 8395A8BA109708B2
1 changed files with 7 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
passes/cmds/connwrappers.cc
View File

@ -65,15 +65,13 @@ struct ConnwrappersWorker
decls[key] = decl;
}
void work(RTLIL::Design *design, RTLIL::Module *module)
void work(RTLIL::Module *module)
{
std::map<RTLIL::SigBit, std::pair<bool, RTLIL::SigSpec>> extend_map;
SigMap sigmap(module);
for (auto &it : module->cells_)
for (auto cell : module->cells())
{
RTLIL::Cell *cell = it.second;
if (!decl_celltypes.count(cell->type))
continue;
@ -105,13 +103,8 @@ struct ConnwrappersWorker
}
}
for (auto &it : module->cells_)
for (auto cell : module->selected_cells())
{
RTLIL::Cell *cell = it.second;
if (!design->selected(module, cell))
continue;
for (auto &conn : cell->connections_)
{
std::vector<RTLIL::SigBit> sigbits = sigmap(conn.second).to_sigbit_vector();
@ -141,8 +134,8 @@ struct ConnwrappersWorker
}
if (old_sig.size())
log("Connected extended bits of %s.%s:%s: %s -> %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name),
RTLIL::id2cstr(conn.first), log_signal(old_sig), log_signal(conn.second));
log("Connected extended bits of %s.%s:%s: %s -> %s\n", log_id(module->name), log_id(cell->name),
log_id(conn.first), log_signal(old_sig), log_signal(conn.second));
}
}
}
@ -200,9 +193,8 @@ struct ConnwrappersPass : public Pass {
log_header(design, "Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n");
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
worker.work(design, mod_it.second);
for (auto module : design->selected_modules())
worker.work(module);
}
} ConnwrappersPass;