mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu
"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
This commit is contained in:
Eddie Hung
GitHub
commit
d61a6b81fc
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@ -30,3 +30,4 @@ $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
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$(eval $(call add_share_file,share,techlibs/common/cells.lib))
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$(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
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$(eval $(call add_share_file,share,techlibs/common/abc9_model.v))
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$(eval $(call add_share_file,share,techlibs/common/cmp2lcu.v))
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@ -0,0 +1,116 @@
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// This pass performs an optimisation that decomposes wide arithmetic
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// comparisons into LUT-size chunks (as guided by the `LUT_WIDTH
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// macro) connected to a single lookahead-carry-unit $lcu cell,
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// which is typically mapped to dedicated (and fast) FPGA
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// carry-chains.
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(* techmap_celltype = "$lt $le $gt $ge" *)
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module _80_lcu_cmp_ (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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parameter Y_WIDTH = 0;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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parameter _TECHMAP_CELLTYPE_ = "";
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generate
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if (_TECHMAP_CELLTYPE_ == "" || `LUT_WIDTH < 2)
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wire _TECHMAP_FAIL_ = 1;
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else if (_TECHMAP_CELLTYPE_ == "$lt") begin
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// Transform $lt into $gt by swapping A and B
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$gt #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y));
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end
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else if (_TECHMAP_CELLTYPE_ == "$le") begin
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// Transform $le into $ge by swapping A and B
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$ge #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y));
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end
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else begin
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// Perform sign extension on A and B
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localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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wire [WIDTH-1:0] AA = {{(WIDTH-A_WIDTH){A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
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wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B};
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// For $ge operation, start with the assumption that A and B are
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// equal (propagating this equality if A and B turn out to be so)
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if (_TECHMAP_CELLTYPE_ == "$ge")
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localparam CI = 1'b1;
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else
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localparam CI = 1'b0;
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$__CMP2LCU #(.AB_WIDTH(WIDTH), .AB_SIGNED(A_SIGNED && B_SIGNED), .LCU_WIDTH(1), .BUDGET(`LUT_WIDTH), .CI(CI))
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_TECHMAP_REPLACE_ (.A(AA), .B(BB), .P(1'b1), .G(1'b0), .Y(Y));
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end
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endgenerate
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endmodule
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module $__CMP2LCU (A, B, P, G, Y);
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parameter AB_WIDTH = 0;
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parameter AB_SIGNED = 0;
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parameter LCU_WIDTH = 1;
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parameter BUDGET = 0;
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parameter CI = 0;
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input [AB_WIDTH-1:0] A; // A from original $gt/$ge
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input [AB_WIDTH-1:0] B; // B from original $gt/$ge
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input [LCU_WIDTH-1:0] P; // P of $lcu
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input [LCU_WIDTH-1:0] G; // G of $lcu
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output Y;
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parameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
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parameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
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parameter [LCU_WIDTH-1:0] _TECHMAP_CONSTMSK_P_ = 0;
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generate
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if (AB_WIDTH == 0) begin
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wire [LCU_WIDTH-1:0] CO;
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$lcu #(.WIDTH(LCU_WIDTH)) _TECHMAP_REPLACE_ (.P(P), .G(G), .CI(CI), .CO(CO));
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assign Y = CO[LCU_WIDTH-1];
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end
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else begin
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if (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] && _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0])
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localparam COST = 0;
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else if (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] || _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0])
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localparam COST = 1;
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else
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localparam COST = 2;
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if (BUDGET < COST)
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$__CMP2LCU #(.AB_WIDTH(AB_WIDTH), .AB_SIGNED(AB_SIGNED), .LCU_WIDTH(LCU_WIDTH+1), .BUDGET(`LUT_WIDTH), .CI(CI))
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_TECHMAP_REPLACE_ (.A(A), .B(B), .P({P, 1'b1}), .G({G, 1'b0}), .Y(Y));
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else begin
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wire PP, GG;
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// Bit-wise equality (xnor) of A and B
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assign PP = A[AB_WIDTH-1] ^~ B[AB_WIDTH-1];
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if (AB_SIGNED)
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assign GG = ~A[AB_WIDTH-1] & B[AB_WIDTH-1];
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else if (_TECHMAP_CONSTMSK_P_[LCU_WIDTH-1]) // First compare for LUT if P (and G) is constant
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assign GG = A[AB_WIDTH-1] & ~B[AB_WIDTH-1];
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else
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// Priority "encoder" that checks A[i] == 1'b1 && B[i] == 1'b0
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// from MSB down, deferring to less significant bits if the
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// MSBs are equal
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assign GG = P[0] & (A[AB_WIDTH-1] & ~B[AB_WIDTH-1]);
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if (LCU_WIDTH == 1) begin
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// Propagate only if all pairs are equal
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// (inconclusive evidence to say A >= B)
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wire P_ = P[0] & PP;
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// Generate if any comparisons call for it
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wire G_ = G[0] | GG;
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end
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else begin
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// Propagate only if all pairs are equal
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// (inconclusive evidence to say A >= B)
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wire [LCU_WIDTH-1:0] P_ = {P[LCU_WIDTH-1:1], P[0] & PP};
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// Generate if any comparisons call for it
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wire [LCU_WIDTH-1:0] G_ = {G[LCU_WIDTH-1:1], G[0] | GG};
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end
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$__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
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_TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P_), .G(G_), .Y(Y));
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end
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end
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endgenerate
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endmodule
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@ -57,10 +57,6 @@ function automatic [(1 << `LUT_WIDTH)-1:0] gen_lut;
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o_bit = (lhs > rhs);
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if (operation == 3)
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o_bit = (lhs >= rhs);
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if (operation == 4)
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o_bit = (lhs == rhs);
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if (operation == 5)
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o_bit = (lhs != rhs);
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gen_lut = gen_lut | (o_bit << n);
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end
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end
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@ -75,10 +71,6 @@ generate
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localparam operation = 2;
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if (_TECHMAP_CELLTYPE_ == "$ge")
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localparam operation = 3;
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if (_TECHMAP_CELLTYPE_ == "$eq")
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localparam operation = 4;
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if (_TECHMAP_CELLTYPE_ == "$ne")
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localparam operation = 5;
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if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)
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wire _TECHMAP_FAIL_ = 1;
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@ -225,9 +225,9 @@ struct SynthPass : public ScriptPass
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run("peepopt");
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run("opt_clean");
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if (help_mode)
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run("techmap -map +/cmp2lut.v", " (if -lut)");
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else
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run(stringf("techmap -map +/cmp2lut.v -D LUT_WIDTH=%d", lut));
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run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)");
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else if (lut)
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run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut));
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if (!noalumacc)
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run("alumacc", " (unless -noalumacc)");
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if (!noshare)
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@ -393,8 +393,6 @@ struct SynthXilinxPass : public ScriptPass
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run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
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run("clean", " (skip if '-nosrl' and '-widemux=0')");
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}
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run("techmap -map +/cmp2lut.v -D LUT_WIDTH=" + lut_size_s);
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}
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if (check_label("map_dsp", "(skip if '-nodsp')")) {
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@ -460,6 +458,7 @@ struct SynthXilinxPass : public ScriptPass
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}
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if (check_label("coarse")) {
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run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=" + lut_size_s);
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run("alumacc");
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run("share");
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run("opt");
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@ -0,0 +1,52 @@
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read_verilog <<EOT
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module top(input [12:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
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assign gtu = a > b;
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assign gts = $signed(a) > $signed(b);
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assign ltu = a < b;
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assign lts = $signed(a) < $signed(b);
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assign geu = a >= b;
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assign ges = $signed(a) >= $signed(b);
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assign leu = a <= b;
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assign les = $signed(a) <= $signed(b);
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endmodule
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EOT
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equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=6
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design -load postopt
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select -assert-count 8 t:$lcu r:WIDTH=5 %i
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select -assert-none t:$gt t:$ge t:$lt t:$le
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design -load preopt
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equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=4
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design -load postopt
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select -assert-count 8 t:$lcu r:WIDTH=7 %i
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select -assert-none t:$gt t:$ge t:$lt t:$le
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design -reset
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read_verilog <<EOT
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module top(input [8:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
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wire [13:0] c = {a[8:6], 3'b101, a[5:4], 2'b11, a[3:0]};
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wire [13:0] d = {b[8], 3'b101, b[7:4], 2'b01, b[3:0]};
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assign gtu = c > d;
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assign gts = $signed(c) > $signed(d);
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assign ltu = c < d;
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assign lts = $signed(c) < $signed(d);
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assign geu = c >= d;
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assign ges = $signed(c) >= $signed(d);
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assign leu = c <= d;
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assign les = $signed(c) <= $signed(d);
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endmodule
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EOT
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design -save gold
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equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=5
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design -load postopt
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select -assert-count 8 t:$lcu r:WIDTH=2 %i
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select -assert-none t:$gt t:$ge t:$lt t:$le
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design -load preopt
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equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=3
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design -load postopt
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select -assert-count 8 t:$lcu r:WIDTH=4 %i
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select -assert-none t:$gt t:$ge t:$lt t:$le
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