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Restore count_outputs, move process check to abc

This commit is contained in:
Eddie Hung 2019-12-30 16:29:08 -08:00
parent dbffbeef5c
commit 88b9c8d46d
2 changed files with 13 additions and 11 deletions
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10
passes/techmap/abc9.cc
View File

@ -164,7 +164,7 @@ struct Abc9Pass : public ScriptPass
map_cmd << " " << arg << " " << args[++argidx];
continue;
}
if (arg == "-fast" || /*arg == "-dff" ||*/ arg == "-keepff"
if (arg == "-fast"
/*|| arg == "-nocleanup"*/ || arg == "-showtmp" || arg == "-markgroups"
|| arg == "-nomfs") {
map_cmd << " " << arg;
@ -189,6 +189,14 @@ struct Abc9Pass : public ScriptPass
active_design->selection_stack.emplace_back(false);
for (auto mod : selected_modules) {
if (module->attributes.count(ID(abc9_box_id)))
continue;
if (module->processes.size() > 0) {
log("Skipping module %s as it contains processes.\n", log_id(module));
continue;
}
log_push();
active_design->selection().select(mod);

14
passes/techmap/abc9_map.cc
View File

@ -268,15 +268,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
log_push();
// FIXME:
/*int count_outputs = design->scratchpad_get_int("write_xaiger.num_outputs");
int count_outputs = design->scratchpad_get_int("write_xaiger.num_outputs");
log("Extracted %d AND gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
design->scratchpad_get_int("write_xaiger.num_ands"),
design->scratchpad_get_int("write_xaiger.num_wires"),
design->scratchpad_get_int("write_xaiger.num_inputs"),
count_outputs);
if (count_outputs > 0)*/ {
if (count_outputs > 0) {
std::string buffer;
std::ifstream ifs;
#if 0
@ -965,13 +964,8 @@ struct Abc9MapPass : public Pass {
CellTypes ct(design);
for (auto module : design->selected_modules())
{
if (module->attributes.count(ID(abc9_box_id)))
continue;
if (module->processes.size() > 0) {
log("Skipping module %s as it contains processes.\n", log_id(module));
continue;
}
if (module->processes.size() > 0)
log_error("Module '%s' has processes!\n", log_id(module));
assign_map.set(module);