mirror of https://github.com/YosysHQ/yosys.git
abc9_ops: optimise to not derive unless attribute exists
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d3b53bc495
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@ -102,8 +102,6 @@ void check(RTLIL::Design *design, bool dff_mode)
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auto inst_module = design->module(cell->type);
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if (!inst_module)
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continue;
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if (!inst_module->get_blackbox_attribute())
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continue;
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IdString derived_type;
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Module *derived_module;
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if (cell->parameters.empty()) {
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@ -111,6 +109,10 @@ void check(RTLIL::Design *design, bool dff_mode)
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derived_module = inst_module;
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}
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else {
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// Check potential (since its value may depend on a parameter,
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// but not its existence)
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if (!inst_module->has_attribute(ID::abc9_flop))
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continue;
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derived_type = inst_module->derive(design, cell->parameters);
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derived_module = design->module(derived_type);
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log_assert(derived_module);
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@ -173,8 +175,6 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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auto inst_module = design->module(cell->type);
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if (!inst_module)
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continue;
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if (!inst_module->get_blackbox_attribute())
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continue;
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IdString derived_type;
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Module *derived_module;
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if (cell->parameters.empty()) {
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@ -182,6 +182,10 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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derived_module = inst_module;
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}
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else {
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// Check potential for any one of those three
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// (since its value may depend on a parameter, but not its existence)
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if (!inst_module->has_attribute(ID::abc9_flop) && !inst_module->has_attribute(ID::abc9_box) && !inst_module->get_bool_attribute(ID::abc9_bypass))
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continue;
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derived_type = inst_module->derive(design, cell->parameters);
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derived_module = design->module(derived_type);
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}
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