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abc9_ops: move assert
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@ -263,9 +263,9 @@ void prep_bypass(RTLIL::Design *design)
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auto derived_type = inst_module->derive(design, cell->parameters);
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inst_module = design->module(derived_type);
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log_assert(inst_module);
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log_assert(!inst_module->get_blackbox_attribute(true /* ignore_wb */));
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if (!inst_module->get_bool_attribute(ID::abc9_bypass))
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continue;
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log_assert(!inst_module->get_blackbox_attribute(true /* ignore_wb */));
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// The idea is to create two techmap designs, one which maps:
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