mirror of https://github.com/YosysHQ/yosys.git
memory_collect: Copy attr from RTLIL::Memory to cell
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
parent
9ee3c57e46
commit
7ff5d6d30a
|
@ -218,6 +218,10 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
|
|||
mem->setPort("\\RD_DATA", sig_rd_data);
|
||||
mem->setPort("\\RD_EN", sig_rd_en);
|
||||
|
||||
// Copy attributes from RTLIL memory to $mem
|
||||
for (auto attr : memory->attributes)
|
||||
mem->attributes[attr.first] = attr.second;
|
||||
|
||||
for (auto c : memcells)
|
||||
module->remove(c);
|
||||
|
||||
|
|
Loading…
Reference in New Issue