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opt_expr: remove redundant
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213a895589
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@ -682,9 +682,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
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RTLIL::SigSpec sig_co = cell->getPort(ID(CO));
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if (sig_ci.wire || sig_bi.wire)
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goto next_cell;
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bool sub = (sig_ci == State::S1 && sig_bi == State::S1);
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// If not a subtraction, yet there is a carry or B is inverted
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