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Merge pull request #1949 from YosysHQ/eddie/select_blackbox 

select: do not select inside black-/white- boxes unless '=' prefix used
This commit is contained in:
Eddie Hung 2020-04-22 15:35:05 -07:00 committed by GitHub
parent 274098cce6 beb9e4b299
commit fa9df06c9d
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 54 additions and 9 deletions
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35
passes/cmds/select.cc
View File

@ -630,8 +630,10 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
std::string arg_mod, arg_memb;
std::unordered_map<std::string, bool> arg_mod_found;
std::unordered_map<std::string, bool> arg_memb_found;
auto isalpha = [](const char &x) { return ((x >= 'a' && x <= 'z') || (x >= 'A' && x <= 'Z')); };
bool prefixed = GetSize(arg) >= 2 && isalpha(arg[0]) && arg[1] == ':';
auto isprefixed = [](const string &s) {
return GetSize(s) >= 2 && ((s[0] >= 'a' && s[0] <= 'z') || (s[0] >= 'A' && s[0] <= 'Z')) && s[1] == ':';
};
if (arg.size() == 0)
return;
@ -759,31 +761,40 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
return;
}
bool select_blackboxes = false;
if (arg.substr(0, 1) == "=") {
arg = arg.substr(1);
select_blackboxes = true;
}
if (!design->selected_active_module.empty()) {
arg_mod = design->selected_active_module;
arg_memb = arg;
if (!prefixed) arg_memb_found[arg_memb] = false;
if (!isprefixed(arg_memb))
arg_memb_found[arg_memb] = false;
} else
if (prefixed && arg[0] >= 'a' && arg[0] <= 'z') {
if (isprefixed(arg) && arg[0] >= 'a' && arg[0] <= 'z') {
arg_mod = "*", arg_memb = arg;
} else {
size_t pos = arg.find('/');
if (pos == std::string::npos) {
arg_mod = arg;
if (!prefixed) arg_mod_found[arg_mod] = false;
if (!isprefixed(arg_mod))
arg_mod_found[arg_mod] = false;
} else {
arg_mod = arg.substr(0, pos);
if (!prefixed) arg_mod_found[arg_mod] = false;
if (!isprefixed(arg_mod))
arg_mod_found[arg_mod] = false;
arg_memb = arg.substr(pos+1);
bool arg_memb_prefixed = GetSize(arg_memb) >= 2 && isalpha(arg_memb[0]) && arg_memb[1] == ':';
if (!arg_memb_prefixed) arg_memb_found[arg_memb] = false;
if (!isprefixed(arg_memb))
arg_memb_found[arg_memb] = false;
}
}
work_stack.push_back(RTLIL::Selection());
RTLIL::Selection &sel = work_stack.back();
if (arg == "*" && arg_mod == "*") {
if (arg == "*" && arg_mod == "*" && select_blackboxes) {
select_filter_active_mod(design, work_stack.back());
return;
}
@ -791,6 +802,9 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
sel.full_selection = false;
for (auto mod : design->modules())
{
if (!select_blackboxes && mod->get_blackbox_attribute())
continue;
if (arg_mod.compare(0, 2, "A:") == 0) {
if (!match_attr(mod->attributes, arg_mod.substr(2)))
continue;
@ -1104,6 +1118,9 @@ struct SelectPass : public Pass {
log(" <obj_pattern>\n");
log(" select the specified object(s) from the current module\n");
log("\n");
log("By default, patterns will not match black/white-box modules or their");
log("contents. To include such objects, prefix the pattern with '='.\n");
log("\n");
log("A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])\n");
log("matching module names, or one of the following:\n");
log("\n");

28
tests/select/blackboxes.ys Normal file
View File

@ -0,0 +1,28 @@
read_verilog -specify <<EOT
module top(input a, b, output o);
assign o = a & b;
endmodule
(* blackbox *)
module bb(input a, b, output o);
assign o = a | b;
specify
(a => o) = 1;
endspecify
endmodule
(* whitebox *)
module wb(input a, b, output o);
assign o = a ^ b;
endmodule
EOT
clean
select -assert-count 1 c:*
select -assert-none t:* t:$and %d
select -assert-count 3 w:*
select -assert-count 4 *
select -assert-count 3 =c:*
select -assert-count 10 =w:*
select -assert-count 13 =*