From 47c8ee7fe4c4935a11ed81b3d94069664e026dca Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 16 Apr 2020 12:23:34 -0700 Subject: [PATCH 1/6] select: do not select inside blackboxes --- passes/cmds/select.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index b64b077e4..b4f3b921a 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -809,6 +809,9 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp continue; } + if (mod->get_blackbox_attribute()) + continue; + if (arg_memb.compare(0, 2, "w:") == 0) { for (auto wire : mod->wires()) if (match_ids(wire->name, arg_memb.substr(2))) From 2ddfb61e65bb8299ba9bc09af9bb4636efc2ddb0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 16 Apr 2020 12:45:04 -0700 Subject: [PATCH 2/6] select: add test for not selecting inside black/white boxes --- tests/select/blackboxes.ys | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 tests/select/blackboxes.ys diff --git a/tests/select/blackboxes.ys b/tests/select/blackboxes.ys new file mode 100644 index 000000000..0031de194 --- /dev/null +++ b/tests/select/blackboxes.ys @@ -0,0 +1,21 @@ +read_verilog -specify < o) = 1; +endspecify +endmodule + +(* whitebox *) +module wb(input a, b, output o); +assign o = a ^ b; +endmodule +EOT + +select -assert-count 1 c:* +select -assert-none t:* t:$and %d From d834cc7afb818924c73ced36b20fe6848b06d999 Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Tue, 21 Apr 2020 14:23:24 +0200 Subject: [PATCH 3/6] Add '=' selection pattern prefix for non-blackbox only patterns Signed-off-by: Claire Wolf --- passes/cmds/select.cc | 38 ++++++++++++++++++++++++++------------ 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index b4f3b921a..889027600 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -630,8 +630,10 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp std::string arg_mod, arg_memb; std::unordered_map arg_mod_found; std::unordered_map arg_memb_found; - auto isalpha = [](const char &x) { return ((x >= 'a' && x <= 'z') || (x >= 'A' && x <= 'Z')); }; - bool prefixed = GetSize(arg) >= 2 && isalpha(arg[0]) && arg[1] == ':'; + + auto isprefixed = [](const string &s) { + return GetSize(s) >= 2 && ((s[0] >= 'a' && s[0] <= 'z') || (s[0] >= 'A' && s[0] <= 'Z')) && s[1] == ':'; + }; if (arg.size() == 0) return; @@ -759,31 +761,40 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp return; } + bool select_blackboxes = true; + if (arg.substr(0, 1) == "=") { + arg = arg.substr(1); + select_blackboxes = false; + } + if (!design->selected_active_module.empty()) { arg_mod = design->selected_active_module; arg_memb = arg; - if (!prefixed) arg_memb_found[arg_memb] = false; + if (!isprefixed(arg_memb)) + arg_memb_found[arg_memb] = false; } else - if (prefixed && arg[0] >= 'a' && arg[0] <= 'z') { + if (isprefixed(arg) && arg[0] >= 'a' && arg[0] <= 'z') { arg_mod = "*", arg_memb = arg; } else { size_t pos = arg.find('/'); if (pos == std::string::npos) { arg_mod = arg; - if (!prefixed) arg_mod_found[arg_mod] = false; + if (!isprefixed(arg_mod)) + arg_mod_found[arg_mod] = false; } else { arg_mod = arg.substr(0, pos); - if (!prefixed) arg_mod_found[arg_mod] = false; + if (!isprefixed(arg_mod)) + arg_mod_found[arg_mod] = false; arg_memb = arg.substr(pos+1); - bool arg_memb_prefixed = GetSize(arg_memb) >= 2 && isalpha(arg_memb[0]) && arg_memb[1] == ':'; - if (!arg_memb_prefixed) arg_memb_found[arg_memb] = false; + if (!isprefixed(arg_memb)) + arg_memb_found[arg_memb] = false; } } work_stack.push_back(RTLIL::Selection()); RTLIL::Selection &sel = work_stack.back(); - if (arg == "*" && arg_mod == "*") { + if (arg == "*" && arg_mod == "*" && select_blackboxes) { select_filter_active_mod(design, work_stack.back()); return; } @@ -791,6 +802,9 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp sel.full_selection = false; for (auto mod : design->modules()) { + if (!select_blackboxes && mod->get_blackbox_attribute()) + continue; + if (arg_mod.compare(0, 2, "A:") == 0) { if (!match_attr(mod->attributes, arg_mod.substr(2))) continue; @@ -809,9 +823,6 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp continue; } - if (mod->get_blackbox_attribute()) - continue; - if (arg_memb.compare(0, 2, "w:") == 0) { for (auto wire : mod->wires()) if (match_ids(wire->name, arg_memb.substr(2))) @@ -1113,6 +1124,9 @@ struct SelectPass : public Pass { log(" all modules with a name matching the given pattern\n"); log(" (i.e. 'N:' is optional as it is the default matching rule)\n"); log("\n"); + log("Prefix the pattern with '=' if the pattern should not match blackbox\n"); + log("modules and their content.\n"); + log("\n"); log("An can be an object name, wildcard expression, or one of\n"); log("the following:\n"); log("\n"); From eaa5a3e786e7ebc5ad25ebd08e7e42f5a5337b5c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 22 Apr 2020 10:15:56 -0700 Subject: [PATCH 4/6] select: do not select black/white boxes by default, '=' prefix to do so --- passes/cmds/select.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 889027600..0f0fe575f 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -761,10 +761,10 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp return; } - bool select_blackboxes = true; + bool select_blackboxes = false; if (arg.substr(0, 1) == "=") { arg = arg.substr(1); - select_blackboxes = false; + select_blackboxes = true; } if (!design->selected_active_module.empty()) { @@ -1113,6 +1113,9 @@ struct SelectPass : public Pass { log(" \n"); log(" select the specified object(s) from the current module\n"); log("\n"); + log("Prefix the following patterns with '=' if the pattern should match black-/\n"); + log("white-box modules and their contents.\n"); + log("\n"); log("A can be a module name, wildcard expression (*, ?, [..])\n"); log("matching module names, or one of the following:\n"); log("\n"); @@ -1124,9 +1127,6 @@ struct SelectPass : public Pass { log(" all modules with a name matching the given pattern\n"); log(" (i.e. 'N:' is optional as it is the default matching rule)\n"); log("\n"); - log("Prefix the pattern with '=' if the pattern should not match blackbox\n"); - log("modules and their content.\n"); - log("\n"); log("An can be an object name, wildcard expression, or one of\n"); log("the following:\n"); log("\n"); From 281cd10717448569fe55cb8b6414d4ce22697d4a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 22 Apr 2020 10:16:14 -0700 Subject: [PATCH 5/6] tests: update select black/white-box tests --- tests/select/blackboxes.ys | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tests/select/blackboxes.ys b/tests/select/blackboxes.ys index 0031de194..9bfe92c6b 100644 --- a/tests/select/blackboxes.ys +++ b/tests/select/blackboxes.ys @@ -16,6 +16,13 @@ module wb(input a, b, output o); assign o = a ^ b; endmodule EOT +clean select -assert-count 1 c:* select -assert-none t:* t:$and %d +select -assert-count 3 w:* +select -assert-count 4 * + +select -assert-count 3 =c:* +select -assert-count 10 =w:* +select -assert-count 13 =* From beb9e4b29964cee0ea1eb77a50e7f040e067144d Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Wed, 22 Apr 2020 21:31:32 +0200 Subject: [PATCH 6/6] Update passes/cmds/select.cc Co-Authored-By: Eddie Hung --- passes/cmds/select.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 0f0fe575f..50c1b57f8 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -1113,8 +1113,8 @@ struct SelectPass : public Pass { log(" \n"); log(" select the specified object(s) from the current module\n"); log("\n"); - log("Prefix the following patterns with '=' if the pattern should match black-/\n"); - log("white-box modules and their contents.\n"); + log("By default, patterns will not match black/white-box modules or their"); + log("contents. To include such objects, prefix the pattern with '='.\n"); log("\n"); log("A can be a module name, wildcard expression (*, ?, [..])\n"); log("matching module names, or one of the following:\n");