mirror of https://github.com/YosysHQ/yosys.git
parent
beab15b77c
commit
c2bf11e42a
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@ -177,10 +177,10 @@ struct TechmapWorker
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std::string orig_cell_name;
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pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src));
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orig_cell_name = cell->name.str();
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if (!flatten_mode) {
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for (auto &it : tpl->cells_)
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if (it.first == ID(_TECHMAP_REPLACE_)) {
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orig_cell_name = cell->name.str();
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module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
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break;
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}
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@ -16,3 +16,21 @@ EOT
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techmap -map %techmap
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select -assert-any w:s0.asdf
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select -assert-any c:s0.blah
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read_verilog <<EOT
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module sub(input i, output o, input j);
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wire _TECHMAP_REPLACE_.asdf = i ;
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barfoo _TECHMAP_REPLACE_.blah (i, o, j);
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endmodule
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EOT
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design -stash techmap
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read_verilog <<EOT
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module top(input i, output o);
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sub s0(i, o);
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endmodule
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EOT
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techmap -map %techmap
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select -assert-any w:s0.asdf
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select -assert-any c:s0.blah
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